diff options
| author | Arthur Heymans <arthur@aheymans.xyz> | 2018-06-03 10:39:16 +0200 |
|---|---|---|
| committer | Arthur Heymans <arthur@aheymans.xyz> | 2018-06-05 07:48:58 +0000 |
| commit | 2dcc3a5c68b4bacbe96c1543cc20e5a3425889fb (patch) | |
| tree | 5e17b66c64aa3bb7d811241e1f37e1cebebdf3e7 /src/northbridge/intel/i945/ram_calc.c | |
| parent | 3aa9adba675b894fc7a1db41f9aea98eafeff88b (diff) | |
nb/intel/i945: Switch to POSTCAR_STAGE
Change-Id: Ibbe6aa55a4efe4a2675c757ba2ab2b56055c60ac
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/26785
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/northbridge/intel/i945/ram_calc.c')
| -rw-r--r-- | src/northbridge/intel/i945/ram_calc.c | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/src/northbridge/intel/i945/ram_calc.c b/src/northbridge/intel/i945/ram_calc.c index bc5f9c8c6d..a106d117f2 100644 --- a/src/northbridge/intel/i945/ram_calc.c +++ b/src/northbridge/intel/i945/ram_calc.c @@ -80,9 +80,10 @@ u32 decode_igd_memory_size(const u32 gms) #define ROMSTAGE_RAM_STACK_SIZE 0x5000 -/* setup_stack_and_mtrrs() determines the stack to use after - * cache-as-ram is torn down as well as the MTRR settings to use. */ -void *setup_stack_and_mtrrs(void) +/* platform_enter_postcar() determines the stack to use after + * cache-as-ram is torn down as well as the MTRR settings to use, + * and continues execution in postcar stage. */ +void platform_enter_postcar(void) { struct postcar_frame pcf; uintptr_t top_of_ram; @@ -105,8 +106,7 @@ void *setup_stack_and_mtrrs(void) postcar_frame_add_mtrr(&pcf, top_of_ram - 4*MiB, 4*MiB, MTRR_TYPE_WRBACK); postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 4*MiB, MTRR_TYPE_WRBACK); - /* Save the number of MTRRs to setup. Return the stack location - * pointing to the number of MTRRs. - */ - return postcar_commit_mtrrs(&pcf); + run_postcar_phase(&pcf); + + /* We do not return here. */ } |