diff options
author | Stefan Reinauer <stepan@coresystems.de> | 2008-10-29 04:51:07 +0000 |
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committer | Stefan Reinauer <stepan@openbios.org> | 2008-10-29 04:51:07 +0000 |
commit | 278534d00734a1f4c3f252f11ca234a6517a590b (patch) | |
tree | 8847383901be6363843888dca10c597664624e5b /src/northbridge/intel/i945/pcie_config.c | |
parent | 00a889c8aabd7b731622d5ff0e765f69e158de2b (diff) |
Support for the Intel 945 northbridge.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3703 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/northbridge/intel/i945/pcie_config.c')
-rw-r--r-- | src/northbridge/intel/i945/pcie_config.c | 68 |
1 files changed, 68 insertions, 0 deletions
diff --git a/src/northbridge/intel/i945/pcie_config.c b/src/northbridge/intel/i945/pcie_config.c new file mode 100644 index 0000000000..94a088bf9d --- /dev/null +++ b/src/northbridge/intel/i945/pcie_config.c @@ -0,0 +1,68 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2008 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "i945.h" + +static inline __attribute__ ((always_inline)) +u8 pcie_read_config8(device_t dev, unsigned int where) +{ + unsigned long addr; + addr = DEFAULT_PCIEXBAR | dev | where; + return read8(addr); +} + +static inline __attribute__ ((always_inline)) +u16 pcie_read_config16(device_t dev, unsigned int where) +{ + unsigned long addr; + addr = DEFAULT_PCIEXBAR | dev | where; + return read16(addr); +} + +static inline __attribute__ ((always_inline)) +u32 pcie_read_config32(device_t dev, unsigned int where) +{ + unsigned long addr; + addr = DEFAULT_PCIEXBAR | dev | where; + return read32(addr); +} + +static inline __attribute__ ((always_inline)) +void pcie_write_config8(device_t dev, unsigned int where, u8 value) +{ + unsigned long addr; + addr = DEFAULT_PCIEXBAR | dev | where; + write8(addr, value); +} + +static inline __attribute__ ((always_inline)) +void pcie_write_config16(device_t dev, unsigned int where, u16 value) +{ + unsigned long addr; + addr = DEFAULT_PCIEXBAR | dev | where; + write16(addr, value); +} + +static inline __attribute__ ((always_inline)) +void pcie_write_config32(device_t dev, unsigned int where, u32 value) +{ + unsigned long addr; + addr = DEFAULT_PCIEXBAR | dev | where; + write32(addr, value); +} |