diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2021-01-20 13:00:02 +0100 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2021-01-30 23:13:05 +0000 |
| commit | a6b0922aa1c4f685056d3dab75a3b330b91b36bd (patch) | |
| tree | 7eb7c0e41bc5c6447ff019331d69e9dac90eeb20 /src/northbridge/intel/i945/northbridge.c | |
| parent | 1ac6f8b804b0be461f5254a6bace3a9823177ba3 (diff) | |
nb/intel/i945: Define and use MMCONF_BUS_NUMBER
Change-Id: I5c75409fd3b7b018e402c471cbd856eca20278b7
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49757
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge/intel/i945/northbridge.c')
| -rw-r--r-- | src/northbridge/intel/i945/northbridge.c | 43 |
1 files changed, 1 insertions, 42 deletions
diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c index d2256729e9..e1e35e9b67 100644 --- a/src/northbridge/intel/i945/northbridge.c +++ b/src/northbridge/intel/i945/northbridge.c @@ -12,38 +12,6 @@ #include <cpu/intel/smm_reloc.h> #include "i945.h" -int decode_pcie_bar(u32 *const base, u32 *const len) -{ - *base = 0; - *len = 0; - - struct device *dev = pcidev_on_root(0, 0); - if (!dev) - return 0; - - const u32 pciexbar_reg = pci_read_config32(dev, PCIEXBAR); - - if (!(pciexbar_reg & (1 << 0))) - return 0; - - switch ((pciexbar_reg >> 1) & 3) { - case 0: /* 256MB */ - *base = pciexbar_reg & (0x0f << 28); - *len = 256 * MiB; - return 1; - case 1: /* 128M */ - *base = pciexbar_reg & (0x1f << 27); - *len = 128 * MiB; - return 1; - case 2: /* 64M */ - *base = pciexbar_reg & (0x3f << 26); - *len = 64 * MiB; - return 1; - } - - return 0; -} - static void mch_domain_read_resources(struct device *dev) { uint32_t pci_tolm, tseg_sizek, cbmem_topk, delta_cbmem; @@ -153,9 +121,6 @@ void northbridge_write_smram(u8 smram) pci_write_config8(dev, SMRAM, smram); } - /* TODO We could determine how many PCIe busses we need in - * the bar. For now that number is hardcoded to a max of 64. - */ static struct device_operations pci_domain_ops = { .read_resources = mch_domain_read_resources, .set_resources = mch_domain_set_resources, @@ -165,15 +130,9 @@ static struct device_operations pci_domain_ops = { static void mc_read_resources(struct device *dev) { - u32 pcie_config_base, pcie_config_len; - pci_dev_read_resources(dev); - if (decode_pcie_bar(&pcie_config_base, &pcie_config_len)) { - const int buses = pcie_config_len / MiB; - struct resource *resource = new_resource(dev, PCIEXBAR); - mmconf_resource_init(resource, pcie_config_base, buses); - } + mmconf_resource(dev, PCIEXBAR); } static struct device_operations mc_ops = { |