diff options
| author | Stefan Reinauer <stepan@coresystems.de> | 2009-03-11 16:20:39 +0000 |
|---|---|---|
| committer | Stefan Reinauer <stepan@openbios.org> | 2009-03-11 16:20:39 +0000 |
| commit | 30140a59f7c34b583b670401a205338e0c8e3311 (patch) | |
| tree | 07b6d6f8c10c804ae3d0e0e9b6eb6f73511a29d7 /src/northbridge/intel/i945/northbridge.c | |
| parent | d229677b6191868661676658d84d7325d8f69f23 (diff) | |
i945 northbridge update
- lots of PCIe updates
- various bug fixes to early init
- some fixes for typos and warnings
- initial support for PCIe x16
- some minor fixes to memory init code
- some subsystem vendor id patches, to be consistent with ICH7
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3997 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/northbridge/intel/i945/northbridge.c')
| -rw-r--r-- | src/northbridge/intel/i945/northbridge.c | 13 |
1 files changed, 9 insertions, 4 deletions
diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c index ad1d938710..81fd58e07f 100644 --- a/src/northbridge/intel/i945/northbridge.c +++ b/src/northbridge/intel/i945/northbridge.c @@ -224,8 +224,8 @@ static void mc_read_resources(device_t dev) resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; - printk_debug("Adding PCIe enhanced config space BAR 0x%08x-0x%08x.\n", - resource->base, (resource->base + resource->size)); + printk_debug("Adding PCIe enhanced config space BAR 0x%08lx-0x%08lx.\n", + (unsigned long)(resource->base), (unsigned long)(resource->base + resource->size)); } static void mc_set_resources(device_t dev) @@ -245,8 +245,13 @@ static void mc_set_resources(device_t dev) static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device) { - pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, - ((device & 0xffff) << 16) | (vendor & 0xffff)); + if (!vendor || !device) { + pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, + pci_read_config32(dev, PCI_VENDOR_ID)); + } else { + pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, + ((device & 0xffff) << 16) | (vendor & 0xffff)); + } } static struct pci_operations intel_pci_ops = { |