diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2020-06-11 14:13:33 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2020-07-22 14:51:39 +0000 |
| commit | 3580d816e6d7a08434d91e9e1acdb94a47f07836 (patch) | |
| tree | 05f09f89f19c110c9c05078eb82852d160f0af5b /src/northbridge/intel/i945/memmap.c | |
| parent | ce55b36c999a0d7c9e47418f81df4566a813670d (diff) | |
nb/intel/i945: Put names to northbridge PCI devices
Tested with BUILD_TIMELESS=1, Getac P470 does not change.
Change-Id: I0d51f48f0c1e37c41322a0eda49806925d9d194d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42285
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge/intel/i945/memmap.c')
| -rw-r--r-- | src/northbridge/intel/i945/memmap.c | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/src/northbridge/intel/i945/memmap.c b/src/northbridge/intel/i945/memmap.c index 07aea98d17..c92e4662d6 100644 --- a/src/northbridge/intel/i945/memmap.c +++ b/src/northbridge/intel/i945/memmap.c @@ -36,20 +36,20 @@ static uintptr_t northbridge_get_tseg_base(void) { uintptr_t tom; - if (pci_read_config8(PCI_DEV(0, 0x0, 0), DEVEN) & (DEVEN_D2F0 | DEVEN_D2F1)) + if (pci_read_config8(HOST_BRIDGE, DEVEN) & (DEVEN_D2F0 | DEVEN_D2F1)) /* IGD enabled, get top of Memory from BSM register */ - tom = pci_read_config32(PCI_DEV(0, 2, 0), BSM); + tom = pci_read_config32(IGD_DEV, BSM); else - tom = (pci_read_config8(PCI_DEV(0, 0, 0), TOLUD) & 0xf7) << 24; + tom = (pci_read_config8(HOST_BRIDGE, TOLUD) & 0xf7) << 24; /* subtract TSEG size */ - tom -= decode_tseg_size(pci_read_config8(PCI_DEV(0, 0, 0), ESMRAMC)); + tom -= decode_tseg_size(pci_read_config8(HOST_BRIDGE, ESMRAMC)); return tom; } static size_t northbridge_get_tseg_size(void) { - const u8 esmramc = pci_read_config8(PCI_DEV(0, 0, 0), ESMRAMC); + const u8 esmramc = pci_read_config8(HOST_BRIDGE, ESMRAMC); return decode_tseg_size(esmramc); } |