diff options
| author | Arthur Heymans <arthur@aheymans.xyz> | 2019-11-12 20:37:21 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-11-15 16:45:36 +0000 |
| commit | dc584c3f221bb59ee6b89e5517617b9d1d74bcf3 (patch) | |
| tree | eb17076271066e5c271742227f76720b28da6d16 /src/northbridge/intel/i945/i945.h | |
| parent | bf53acca5e9c6b61086e42eb9e73fd4bb59a6f31 (diff) | |
nb/intel/i945: Move boilerplate romstage to a common location
This adds callbacks for mainboard specific init.
Change-Id: Ib67bc492a7b7f02f9b57a52fd6730e16501b436e
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36787
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge/intel/i945/i945.h')
| -rw-r--r-- | src/northbridge/intel/i945/i945.h | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/src/northbridge/intel/i945/i945.h b/src/northbridge/intel/i945/i945.h index 4dd5379469..e9e6f4d094 100644 --- a/src/northbridge/intel/i945/i945.h +++ b/src/northbridge/intel/i945/i945.h @@ -375,6 +375,18 @@ void sdram_dump_mchbar_registers(void); u32 decode_igd_memory_size(u32 gms); u32 decode_tseg_size(const u8 esmramc); +/* Romstage mainboard callbacks */ +/* Optional: Override the default LPC config. */ +void mainboard_lpc_decode(void); +/* Optional: Initialize the superio for serial output. */ +void mainboard_superio_config(void); +/* Optional: mainboard specific init after console init and before raminit. */ +void mainboard_pre_raminit_config(int s3_resume); +/* Mainboard specific RCBA init. Happens after raminit. */ +void mainboard_late_rcba_config(void); +/* Optional: mainboard callback to get SPD map */ +void mainboard_get_spd_map(u8 spd_map[4]); + #endif /* __ACPI__ */ #endif /* NORTHBRIDGE_INTEL_I945_H */ |