diff options
| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-09-30 04:14:19 +0300 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-10-05 13:21:00 +0000 |
| commit | ad787e18e0ed24495132d0e9e638ed835afad354 (patch) | |
| tree | 9ee07a78a871830740879127c7c3f14094a57dd1 /src/northbridge/intel/i945/i945.h | |
| parent | 81ade745b19194fbad3e3d51d0dac6ca76de1f01 (diff) | |
intel/i945,i82801gx: Refactor early PCI bridge reset
Change-Id: Ibd5cd2afc8e41cc50abdda0fb7d063073c3acdc1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35678
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge/intel/i945/i945.h')
| -rw-r--r-- | src/northbridge/intel/i945/i945.h | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/src/northbridge/intel/i945/i945.h b/src/northbridge/intel/i945/i945.h index d19748eaf9..69a6413f42 100644 --- a/src/northbridge/intel/i945/i945.h +++ b/src/northbridge/intel/i945/i945.h @@ -83,8 +83,6 @@ /* Device 0:1.0 PCI configuration space (PCI Express) */ #define PCISTS1 0x06 /* 16bit */ -#define SBUSN1 0x19 /* 8bit */ -#define SUBUSN1 0x1a /* 8bit */ #define SSTS1 0x1e /* 16bit */ #define PEG_CAP 0xa2 /* 16bit */ #define DSTS 0xaa /* 16bit */ |