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authorKyösti Mälkki <kyosti.malkki@gmail.com>2019-03-05 07:54:28 +0200
committerNico Huber <nico.h@gmx.de>2019-03-06 11:54:17 +0000
commit503d3247e48d803ce36e98d2064cf22220bb0dfd (patch)
treef50d79bf985fdcf6489178ffdc9918d1f0759183 /src/northbridge/intel/i945/i945.h
parente079e5ccc2e707e5b6bd3b011e04c9138f159808 (diff)
Remove DEFAULT_PCIEXBAR alias
The other DEFAULT_ entries are just immediate constants. Change-Id: Iebf4266810b8210cebabc814bba2776638d9b74d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31758 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/northbridge/intel/i945/i945.h')
-rw-r--r--src/northbridge/intel/i945/i945.h1
1 files changed, 0 insertions, 1 deletions
diff --git a/src/northbridge/intel/i945/i945.h b/src/northbridge/intel/i945/i945.h
index 0db07e1caf..8c082416bc 100644
--- a/src/northbridge/intel/i945/i945.h
+++ b/src/northbridge/intel/i945/i945.h
@@ -17,7 +17,6 @@
#define NORTHBRIDGE_INTEL_I945_H
/* Northbridge BARs */
-#define DEFAULT_PCIEXBAR CONFIG_MMCONF_BASE_ADDRESS /* 4 KB per PCIe device */
#define DEFAULT_X60BAR 0xfed13000
#ifndef __ACPI__
#define DEFAULT_MCHBAR ((u8 *)0xfed14000) /* 16 KB */