diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2018-11-24 10:26:04 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2018-11-25 20:02:40 +0000 |
| commit | a6634f1f78da9d05082f94f2c86f5ab15adf0d40 (patch) | |
| tree | 9119175ccd82a34f73f5c28a2eb740c9fb553eb1 /src/northbridge/intel/i945/i945.h | |
| parent | a9068aa4e058a72b0cdeaffa423db17d7dd09fc6 (diff) | |
nb/intel/i945: Add and use defines for registers of device 0:01.0
Some registers are not documented in "Mobile Intel 945 Express
Chipset Family" datasheet but they are in "Intel 945G/945GZ/
945GC/945P/945PL Express Chipset Family" datasheet.
Change-Id: I81f68a5b16e195626d4d271f8c7036032611bea3
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/29824
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src/northbridge/intel/i945/i945.h')
| -rw-r--r-- | src/northbridge/intel/i945/i945.h | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/src/northbridge/intel/i945/i945.h b/src/northbridge/intel/i945/i945.h index cc5f08791f..65a40e7268 100644 --- a/src/northbridge/intel/i945/i945.h +++ b/src/northbridge/intel/i945/i945.h @@ -83,7 +83,24 @@ /* Device 0:1.0 PCI configuration space (PCI Express) */ +#define PCISTS1 0x06 /* 16bit */ +#define SBUSN1 0x19 /* 8bit */ +#define SUBUSN1 0x1a /* 8bit */ +#define SSTS1 0x1e /* 16bit */ #define BCTRL1 0x3e /* 16bit */ +#define PEG_CAP 0xa2 /* 16bit */ +#define DSTS 0xaa /* 16bit */ +#define SLOTCAP 0xb4 /* 32bit */ +#define SLOTSTS 0xba /* 16bit */ +#define PEG_LC 0xec /* 32bit */ +#define PVCCAP1 0x104 /* 32bit */ +#define VC0RCTL 0x114 /* 32bit */ +#define LE1D 0x150 /* 32bit */ +#define LE1A 0x158 /* 64bit */ +#define UESTS 0x1c4 /* 32bit */ +#define CESTS 0x1d0 /* 32bit */ +#define PEGTC 0x204 /* 32bit */ +#define PEGCC 0x208 /* 32bit */ #define PEGSTS 0x214 /* 32bit */ |