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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2016-07-22 22:53:19 +0300 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2016-12-11 08:57:17 +0100 |
| commit | 823020d56be1bf6425b4e433a1f1c2bbc2c4c90b (patch) | |
| tree | 83bcc59a0c5c8f77322b846018d1ba84edb74566 /src/northbridge/intel/i945/early_init.c | |
| parent | 811932a61411f5258096e734a158be01c00cf940 (diff) | |
intel i945 gm45 x4x post-car: Use postcar_frame for MTRR setup
Adapt implementation from skylake to prepare for removal of
HIGH_MEMORY_SAVE and moving on to RELOCATABLE_RAMSTAGE.
With this change, CBMEM region is set early-on as WRBACK
with MTRRs and romstage ram stack is moved to CBMEM.
Change-Id: Idee5072fd499aa3815b0d78f54308c273e756fd1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15791
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/northbridge/intel/i945/early_init.c')
| -rw-r--r-- | src/northbridge/intel/i945/early_init.c | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index 16ae55f68a..8ebb422551 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -905,7 +905,6 @@ static void i945_prepare_resume(int s3resume) * this is not a resume. In that case we just create the cbmem toc. */ if (s3resume && cbmem_was_initted) { - acpi_prepare_for_resume(); /* Magic for S3 resume */ pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, |