diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2021-01-20 13:00:02 +0100 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2021-01-30 23:13:05 +0000 |
| commit | a6b0922aa1c4f685056d3dab75a3b330b91b36bd (patch) | |
| tree | 7eb7c0e41bc5c6447ff019331d69e9dac90eeb20 /src/northbridge/intel/i945/bootblock.c | |
| parent | 1ac6f8b804b0be461f5254a6bace3a9823177ba3 (diff) | |
nb/intel/i945: Define and use MMCONF_BUS_NUMBER
Change-Id: I5c75409fd3b7b018e402c471cbd856eca20278b7
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49757
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge/intel/i945/bootblock.c')
| -rw-r--r-- | src/northbridge/intel/i945/bootblock.c | 16 |
1 files changed, 13 insertions, 3 deletions
diff --git a/src/northbridge/intel/i945/bootblock.c b/src/northbridge/intel/i945/bootblock.c index 60051babd3..f4b46282ca 100644 --- a/src/northbridge/intel/i945/bootblock.c +++ b/src/northbridge/intel/i945/bootblock.c @@ -1,13 +1,23 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <arch/bootblock.h> +#include <assert.h> #include <device/pci_ops.h> +#include <types.h> #include "i945.h" -void bootblock_early_northbridge_init(void) +static uint32_t encode_pciexbar_length(void) { - uint32_t reg; + switch (CONFIG_MMCONF_BUS_NUMBER) { + case 256: return 0 << 1; + case 128: return 1 << 1; + case 64: return 2 << 1; + default: return dead_code_t(uint32_t); + } +} +void bootblock_early_northbridge_init(void) +{ /* * The "io" variant of the config access is explicitly used to setup the PCIEXBAR * because CONFIG(MMCONF_SUPPORT) is set to true. That way all subsequent non-explicit @@ -17,6 +27,6 @@ void bootblock_early_northbridge_init(void) * * The PCIEXBAR is assumed to live in the memory mapped IO space under 4GiB. */ - reg = CONFIG_MMCONF_BASE_ADDRESS | 4 | 1; /* 64MiB - 0-63 buses. */ + const uint32_t reg = CONFIG_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1; pci_io_write_config32(HOST_BRIDGE, PCIEXBAR, reg); } |