* drop ich7 include

* detect more i945 variants
* raminit fixes
* ACPI + PCIe updates

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4455 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

3 files changed, 372 insertions, 84 deletions

diff --git a/src/northbridge/intel/i945/acpi/i945.asl b/src/northbridge/intel/i945/acpi/i945.asl
index e6ba95d00d..49986f9cef 100644
--- a/src/northbridge/intel/i945/acpi/i945.asl
+++ b/src/northbridge/intel/i945/acpi/i945.asl
@@ -26,35 +26,50 @@ Device (PDRC)
 {
 	Name (_HID, EISAID("PNP0C02"))
 	Name (_UID, 1)
+
+	// This does not seem to work correctly yet - set values statically for
+	// now.
+	
+	//Name (PDRS, ResourceTemplate() {
+	//	Memory32Fixed(ReadWrite, 0x00000000, 0x00004000, RCRB) // RCBA
+	//	Memory32Fixed(ReadWrite, 0x00000000, 0x00004000, MCHB) // MCHBAR
+	//	Memory32Fixed(ReadWrite, 0x00000000, 0x00001000, DMIB) // DMIBAR
+	//	Memory32Fixed(ReadWrite, 0x00000000, 0x00001000, EGPB) // EPBAR
+	//	Memory32Fixed(ReadWrite, 0x00000000, 0x00000000, PCIE) // PCIE BAR
+	//	Memory32Fixed(ReadWrite, 0xfed20000, 0x00070000, ICHB) // Misc ICH
+	//})
+
 	Name (PDRS, ResourceTemplate() {
-		Memory32Fixed(ReadWrite, 0x00000000, 0x00004000, RCRB) // RCBA
-		Memory32Fixed(ReadWrite, 0x00000000, 0x00004000, MCHB) // MCHBAR
-		Memory32Fixed(ReadWrite, 0x00000000, 0x00001000, DMIB) // DMIBAR
-		Memory32Fixed(ReadWrite, 0x00000000, 0x00001000, EGPB) // EPBAR
-		Memory32Fixed(ReadWrite, 0x00000000, 0x00000000, PCIE) // PCIE BAR
-		Memory32Fixed(ReadWrite, 0xfed20000, 0x00070000, ICHB) // Misc ICH
+		Memory32Fixed(ReadWrite, 0xfed1c000, 0x00004000) // RCBA
+		Memory32Fixed(ReadWrite, 0xfed14000, 0x00004000) // MCHBAR
+		Memory32Fixed(ReadWrite, 0xfed18000, 0x00001000) // DMIBAR
+		Memory32Fixed(ReadWrite, 0xfed19000, 0x00001000) // EPBAR
+		Memory32Fixed(ReadWrite, 0xf0000000, 0x04000000) // PCIE BAR
+		Memory32Fixed(ReadWrite, 0xfed20000, 0x00020000) // Misc ICH
+		Memory32Fixed(ReadWrite, 0xfed40000, 0x00005000) // Misc ICH
+		Memory32Fixed(ReadWrite, 0xfed45000, 0x0004b000) // Misc ICH
 	})
 
 	// Current Resource Settings
 	Method (_CRS, 0, Serialized)
 	{
-		CreateDwordField(PDRS, ^RCRB._BAS, RBR0)
-		ShiftLeft(\_SB.PCI0.LPCB.RCBA, 14, RBR0)
+		//CreateDwordField(PDRS, ^RCRB._BAS, RBR0)
+		//ShiftLeft(\_SB.PCI0.LPCB.RCBA, 14, RBR0)
 
-		CreateDwordField(PDRS, ^MCHB._BAS, MBR0)
-		ShiftLeft(\_SB.PCI0.MCHC.MHBR, 14, MBR0)
+		//CreateDwordField(PDRS, ^MCHB._BAS, MBR0)
+		//ShiftLeft(\_SB.PCI0.MCHC.MHBR, 14, MBR0)
 
-		CreateDwordField(PDRS, ^DMIB._BAS, DBR0)
-		ShiftLeft(\_SB.PCI0.MCHC.DMBR, 12, DBR0)
+		//CreateDwordField(PDRS, ^DMIB._BAS, DBR0)
+		//ShiftLeft(\_SB.PCI0.MCHC.DMBR, 12, DBR0)
 
-		CreateDwordField(PDRS, ^EGPB._BAS, EBR0)
-		ShiftLeft(\_SB.PCI0.MCHC.EPBR, 12, EBR0)
+		//CreateDwordField(PDRS, ^EGPB._BAS, EBR0)
+		//ShiftLeft(\_SB.PCI0.MCHC.EPBR, 12, EBR0)
 
-		CreateDwordField(PDRS, ^PCIE._BAS, PBR0)
-		ShiftLeft(\_SB.PCI0.MCHC.PXBR, 26, PBR0)
+		//CreateDwordField(PDRS, ^PCIE._BAS, PBR0)
+		//ShiftLeft(\_SB.PCI0.MCHC.PXBR, 26, PBR0)
 
-		CreateDwordField(PDRS, ^PCIE._LEN, PSZ0)
-		ShiftLeft(0x10000000, \_SB.PCI0.MCHC.PXSZ, PSZ0)
+		//CreateDwordField(PDRS, ^PCIE._LEN, PSZ0)
+		//ShiftLeft(0x10000000, \_SB.PCI0.MCHC.PXSZ, PSZ0)
 
 		Return(PDRS)
 	}
diff --git a/src/northbridge/intel/i945/acpi/i945_hostbridge.asl b/src/northbridge/intel/i945/acpi/i945_hostbridge.asl
index 01f04b8162..d889b38524 100644
--- a/src/northbridge/intel/i945/acpi/i945_hostbridge.asl
+++ b/src/northbridge/intel/i945/acpi/i945_hostbridge.asl
@@ -35,18 +35,18 @@ Device (MCHC)
 		,	11,	//
 		EPBR,	20,	// EPBAR
 
-		Offset (0x48),	// MCHBAR
+		Offset (0x44),	// MCHBAR
 		MHEN,	 1,	// Enable
 		,	13,	//
 		MHBR,	18,	// MCHBAR
 
-		Offset (0x60),	// PCIe BAR
+		Offset (0x48),	// PCIe BAR
 		PXEN,	 1,	// Enable
 		PXSZ,	 2,	// BAR size
 		,	23,	//
 		PXBR,	 6,	// PCIe BAR
 
-		Offset (0x68),	// DMIBAR
+		Offset (0x4c),	// DMIBAR
 		DMEN,	 1,	// Enable
 		,	11,	//
 		DMBR,	20,	// DMIBAR
@@ -87,11 +87,13 @@ Device (MCHC)
 		,	 2,
 		PM6H,	 2,
 		,	 2,
-		Offset (0xa2),	// Top of upper used dram
-		TUUD,	16,
-		Offset (0xb0),
-		,	 4,
-		TLUD,	12	// TOLUD
+
+		Offset (0x9c),	// Top of Low Used Memory
+		,	 3,
+		TLUD,	 5,
+
+		Offset (0xa0),	// Top of Used Memory
+		TOM,	16,
 	}
 
 }
@@ -172,11 +174,29 @@ Method (_CRS, 0, Serialized)
 				0x00000000, 0x000dc000, 0x000dffff, 0x00000000,
 				0x00004000,,, OPR7)
 
-		// Bios Extension (0xe0000-0xeffff)
+		// BIOS Extension (0xe0000-0xe3fff)
+		DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000e0000, 0x000e3fff, 0x00000000,
+				0x00004000,,, ESG0)
+
+		// BIOS Extension (0xe4000-0xe7fff)
 		DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
 				Cacheable, ReadWrite,
-				0x00000000, 0x000e0000, 0x000effff, 0x00000000,
-				0x00010000,,, ESEG)
+				0x00000000, 0x000e4000, 0x000e7fff, 0x00000000,
+				0x00004000,,, ESG1)
+
+		// BIOS Extension (0xe8000-0xebfff)
+		DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000e8000, 0x000ebfff, 0x00000000,
+				0x00004000,,, ESG2)
+
+		// BIOS Extension (0xec000-0xeffff)
+		DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				Cacheable, ReadWrite,
+				0x00000000, 0x000ec000, 0x000effff, 0x00000000,
+				0x00004000,,, ESG3)
 
 		// System BIOS (0xf0000-0xfffff)
 		DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
@@ -189,6 +209,12 @@ Method (_CRS, 0, Serialized)
 				 Cacheable, ReadWrite,
 				 0x00000000, 0x00000000, 0xfebfffff, 0x00000000,
 				 0x00000000,,, PM01)
+
+		 // TPM Area (0xfed40000-0xfed44fff)
+		 DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
+				 Cacheable, ReadWrite,
+				 0x00000000, 0xfed40000, 0xfed44fff, 0x00000000,
+				 0x00000000,,, TPMR)
 	})
 
 	// Find PCI resource area in MCRS
@@ -197,64 +223,15 @@ Method (_CRS, 0, Serialized)
 	CreateDwordField(MCRS, PM01._LEN, PLEN)
 
 	// Fix up PCI memory region:
-	// Enter actual TOLUD. The TOLUD register contains bits 20-31 of
+	// Enter actual TOLUD. The TOLUD register contains bits 27-31 of
 	// the top of memory address.
-	ShiftLeft (^MCHC.TLUD, 20, PMIN)
+	ShiftLeft (^MCHC.TLUD, 27, PMIN)
 	Add(Subtract(PMAX, PMIN), 1, PLEN)
 
 	Return (MCRS)
 }
 
-// PCI Interrupt Routing
-Method(_PRT)
-{
-	If (PICM) {
-		Return (Package() {
-			// PCIe Graphics		0:1.0
-			Package() { 0x0001ffff, 0, 0, 16 },
-			// Onboard graphics (IGD)	0:2.0
-			Package() { 0x0002ffff, 0, 0, 16 },
-			// High Definition Audio	0:1b.0
-			Package() { 0x001bffff, 0, 0, 16 },
-			// PCIe Root Ports		0:1c.x
-			Package() { 0x001cffff, 0, 0, 16 },
-			Package() { 0x001cffff, 1, 0, 17 },
-			Package() { 0x001cffff, 2, 0, 18 },
-			Package() { 0x001cffff, 3, 0, 19 },
-			// USB and EHCI			0:1d.x
-			Package() { 0x001dffff, 0, 0, 23 },
-			Package() { 0x001dffff, 1, 0, 19 },
-			Package() { 0x001dffff, 2, 0, 18 },
-			Package() { 0x001dffff, 3, 0, 16 },
-			// LPC device			0:1f.0
-			Package() { 0x001fffff, 0, 0, 19 },
-			Package() { 0x001fffff, 1, 0, 19},
-			Package() { 0x001fffff, 2, 0, 19 },
-			Package() { 0x001fffff, 3, 0, 16 }
-		})
-	} Else {
-		Return (Package() {
-			// PCIe Graphics		0:1.0
-			Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
-			// Onboard graphics (IGD)	0:2.0
-			Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 },
-			// High Definition Audio	0:1b.0
-			Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKG, 0 },
-			// PCIe Root Ports		0:1c.x
-			Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKB, 0 },
-			Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKA, 0 },
-			Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
-			Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKD, 0 },
-			// USB and EHCI			0:1d.x
-			Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKH, 0 },
-			Package() { 0x001dffff, 1, \_SB.PCI0.LPCB.LNKD, 0 },
-			Package() { 0x001dffff, 2, \_SB.PCI0.LPCB.LNKC, 0 },
-			// LPC device			0:1f.0
-			Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKD, 0 },
-			Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKD, 0 },
-			Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKD, 0 },
-			Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKA, 0 }
-		})
-	}
+/* IRQ assignment is mainboard specific. Get it from mainboard ACPI code */
+Include ("acpi/i945_pci_irqs.asl")
+
 
-}
diff --git a/src/northbridge/intel/i945/acpi/i945_igd.asl b/src/northbridge/intel/i945/acpi/i945_igd.asl
index 37de874ceb..806ae5dd32 100644
--- a/src/northbridge/intel/i945/acpi/i945_igd.asl
+++ b/src/northbridge/intel/i945/acpi/i945_igd.asl
@@ -23,6 +23,302 @@ Device (GFX0)
 {
 	Name (_ADR, 0x00020000)
 
-	// TODO display switching etc
+	/* Display Output Switching */
+	Method (_DOS, 1)
+	{
+		/* Windows 2000 and Windows XP call _DOS to enable/disable
+		 * Display Output Switching during init and while a switch
+		 * is already active
+		 */
+		Store (And(Arg0, 7), DSEN)
+	}
+
+	/* We try to support as many i945 systems as possible,
+	 * so keep the number of DIDs flexible.
+	 */
+	Method (_DOD, 0)
+	{
+		If (LEqual(NDID, 1)) {
+			Name(DOD1, Package() {
+				0xffffffff
+			})
+			Store (Or(0x00010000, DID1), Index(DOD1, 0))
+			Return(DOD1)
+		}
+
+		If (LEqual(NDID, 2)) {
+			Name(DOD2, Package() {
+				0xffffffff,
+				0xffffffff
+			})
+			Store (Or(0x00010000, DID2), Index(DOD2, 0))
+			Store (Or(0x00010000, DID2), Index(DOD2, 1))
+			Return(DOD2)
+		}
+
+		If (LEqual(NDID, 3)) {
+			Name(DOD3, Package() {
+				0xffffffff,
+				0xffffffff,
+				0xffffffff
+			})
+			Store (Or(0x00010000, DID3), Index(DOD3, 0))
+			Store (Or(0x00010000, DID3), Index(DOD3, 1))
+			Store (Or(0x00010000, DID3), Index(DOD3, 2))
+			Return(DOD3)
+		}
+
+		If (LEqual(NDID, 4)) {
+			Name(DOD4, Package() {
+				0xffffffff,
+				0xffffffff,
+				0xffffffff,
+				0xffffffff
+			})
+			Store (Or(0x00010000, DID4), Index(DOD4, 0))
+			Store (Or(0x00010000, DID4), Index(DOD4, 1))
+			Store (Or(0x00010000, DID4), Index(DOD4, 2))
+			Store (Or(0x00010000, DID4), Index(DOD4, 3))
+			Return(DOD4)
+		}
+
+		If (LGreater(NDID, 4)) {
+			Name(DOD5, Package() {
+				0xffffffff,
+				0xffffffff,
+				0xffffffff,
+				0xffffffff,
+				0xffffffff
+			})
+			Store (Or(0x00010000, DID5), Index(DOD5, 0))
+			Store (Or(0x00010000, DID5), Index(DOD5, 1))
+			Store (Or(0x00010000, DID5), Index(DOD5, 2))
+			Store (Or(0x00010000, DID5), Index(DOD5, 3))
+			Store (Or(0x00010000, DID5), Index(DOD5, 4))
+			Return(DOD5)
+		}
+
+		/* Some error happened, but we have to return something */
+		Return (Package() {0x00000400})
+	}
+	
+	Device(DD01)
+	{
+		/* Device Unique ID */
+		Method(_ADR, 0, Serialized)
+		{
+			If(LEqual(DID1, 0)) {
+				Return (1)
+			} Else {
+				Return (And(0xffff, DID1))
+			}
+		}
+
+		/* Device Current Status */
+		Method(_DCS, 0)
+		{
+			TRAP(1)
+			If (And(CSTE, 1)) {
+				Return (0x1f)
+			}
+			Return(0x1d)
+		}
+
+		/* Query Device Graphics State */
+		Method(_DGS, 0)
+		{
+			If (And(NSTE, 1)) {
+				Return(1)
+			}
+			Return(0)
+		}
+
+		/* Device Set State */
+		Method(_DSS, 1)
+		{
+			/* If Parameter Arg0 is (1 << 31) | (1 << 30), the 
+			 * display switch was completed
+			 */
+			If (LEqual(And(Arg0, 0xc0000000), 0xc0000000)) {
+				Store (NSTE, CSTE)
+			}
+		}
+	}
+
+	Device(DD02)
+	{
+		/* Device Unique ID */
+		Method(_ADR, 0, Serialized)
+		{
+			If(LEqual(DID2, 0)) {
+				Return (2)
+			} Else {
+				Return (And(0xffff, DID2))
+			}
+		}
+
+		/* Device Current Status */
+		Method(_DCS, 0)
+		{
+			TRAP(1)
+			If (And(CSTE, 2)) {
+				Return (0x1f)
+			}
+			Return(0x1d)
+		}
+
+		/* Query Device Graphics State */
+		Method(_DGS, 0)
+		{
+			If (And(NSTE, 2)) {
+				Return(1)
+			}
+			Return(0)
+		}
+
+		/* Device Set State */
+		Method(_DSS, 1)
+		{
+			/* If Parameter Arg0 is (1 << 31) | (1 << 30), the 
+			 * display switch was completed
+			 */
+			If (LEqual(And(Arg0, 0xc0000000), 0xc0000000)) {
+				Store (NSTE, CSTE)
+			}
+		}
+	}
+
+
+	Device(DD03)
+	{
+		/* Device Unique ID */
+		Method(_ADR, 0, Serialized)
+		{
+			If(LEqual(DID3, 0)) {
+				Return (3)
+			} Else {
+				Return (And(0xffff, DID3))
+			}
+		}
+
+		/* Device Current Status */
+		Method(_DCS, 0)
+		{
+			TRAP(1)
+			If (And(CSTE, 4)) {
+				Return (0x1f)
+			}
+			Return(0x1d)
+		}
+
+		/* Query Device Graphics State */
+		Method(_DGS, 0)
+		{
+			If (And(NSTE, 4)) {
+				Return(1)
+			}
+			Return(0)
+		}
+
+		/* Device Set State */
+		Method(_DSS, 1)
+		{
+			/* If Parameter Arg0 is (1 << 31) | (1 << 30), the 
+			 * display switch was completed
+			 */
+			If (LEqual(And(Arg0, 0xc0000000), 0xc0000000)) {
+				Store (NSTE, CSTE)
+			}
+		}
+	}
+
+
+	Device(DD04)
+	{
+		/* Device Unique ID */
+		Method(_ADR, 0, Serialized)
+		{
+			If(LEqual(DID4, 0)) {
+				Return (4)
+			} Else {
+				Return (And(0xffff, DID4))
+			}
+		}
+
+		/* Device Current Status */
+		Method(_DCS, 0)
+		{
+			TRAP(1)
+			If (And(CSTE, 8)) {
+				Return (0x1f)
+			}
+			Return(0x1d)
+		}
+
+		/* Query Device Graphics State */
+		Method(_DGS, 0)
+		{
+			If (And(NSTE, 4)) {
+				Return(1)
+			}
+			Return(0)
+		}
+
+		/* Device Set State */
+		Method(_DSS, 1)
+		{
+			/* If Parameter Arg0 is (1 << 31) | (1 << 30), the 
+			 * display switch was completed
+			 */
+			If (LEqual(And(Arg0, 0xc0000000), 0xc0000000)) {
+				Store (NSTE, CSTE)
+			}
+		}
+	}
+
+
+	Device(DD05)
+	{
+		/* Device Unique ID */
+		Method(_ADR, 0, Serialized)
+		{
+			If(LEqual(DID5, 0)) {
+				Return (5)
+			} Else {
+				Return (And(0xffff, DID5))
+			}
+		}
+
+		/* Device Current Status */
+		Method(_DCS, 0)
+		{
+			TRAP(1)
+			If (And(CSTE, 16)) {
+				Return (0x1f)
+			}
+			Return(0x1d)
+		}
+
+		/* Query Device Graphics State */
+		Method(_DGS, 0)
+		{
+			If (And(NSTE, 4)) {
+				Return(1)
+			}
+			Return(0)
+		}
+
+		/* Device Set State */
+		Method(_DSS, 1)
+		{
+			/* If Parameter Arg0 is (1 << 31) | (1 << 30), the 
+			 * display switch was completed
+			 */
+			If (LEqual(And(Arg0, 0xc0000000), 0xc0000000)) {
+				Store (NSTE, CSTE)
+			}
+		}
+	}
+
 }