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authorUwe Hermann <uwe@hermann-uwe.de>2010-11-22 12:59:36 +0000
committerUwe Hermann <uwe@hermann-uwe.de>2010-11-22 12:59:36 +0000
commit6e9ab97106925f74b993ddf66db0b6525dc71580 (patch)
tree054463939786fb42f43b05d81e6f5b50308f86b8 /src/northbridge/intel/i855/raminit.h
parentabc0c8551604933ca54e9eaa48c3f00e4915dc90 (diff)
i855: Remove useless memctrl indirection.
This needlessly complicates the code and increases register pressure on romcc chipsets. We did the same conversion on i440BX, i830, and others. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Peter Stuge <peter@stuge.se> Acked-by: Stefan Reinauer <stepan@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6112 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/northbridge/intel/i855/raminit.h')
-rw-r--r--src/northbridge/intel/i855/raminit.h9
1 files changed, 2 insertions, 7 deletions
diff --git a/src/northbridge/intel/i855/raminit.h b/src/northbridge/intel/i855/raminit.h
index 2ac0fde62d..8b20c2be64 100644
--- a/src/northbridge/intel/i855/raminit.h
+++ b/src/northbridge/intel/i855/raminit.h
@@ -21,18 +21,13 @@
#ifndef NORTHBRIDGE_INTEL_I855_RAMINIT_H
#define NORTHBRIDGE_INTEL_I855_RAMINIT_H
-/* i855 Northbridge PCI device */
+/* i855 Northbridge PCI devices */
#define NORTHBRIDGE PCI_DEV(0, 0, 0)
#define NORTHBRIDGE_MMC PCI_DEV(0, 0, 1)
/* The i855 supports max. 2 dual-sided SO-DIMMs. */
#define DIMM_SOCKETS 2
-struct mem_controller {
- device_t d0;
- uint16_t channel0[DIMM_SOCKETS];
-};
-
-void sdram_initialize(int controllers, const struct mem_controller *ctrl);
+void sdram_initialize(void);
#endif /* NORTHBRIDGE_INTEL_I855_RAMINIT_H */