diff options
| author | Joseph Smith <joe@settoplinux.org> | 2010-02-01 22:51:18 +0000 |
|---|---|---|
| committer | Joseph Smith <joe@smittys.pointclark.net> | 2010-02-01 22:51:18 +0000 |
| commit | fa742da56be11090fc713c21bc3faf786d99b135 (patch) | |
| tree | 24b75d878f967a7decf4579b121b0f5f51248c25 /src/northbridge/intel/i82830/raminit.h | |
| parent | 14be4d0d521826c0917ff7a42c6c847be5cec85a (diff) | |
Alot of it is trivial clean ups and 830 is now able to initialize one row/side of memory at a time.
Signed-off-by: Joseph Smith <joe@settoplinux.org>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5073 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/northbridge/intel/i82830/raminit.h')
| -rw-r--r-- | src/northbridge/intel/i82830/raminit.h | 11 |
1 files changed, 6 insertions, 5 deletions
diff --git a/src/northbridge/intel/i82830/raminit.h b/src/northbridge/intel/i82830/raminit.h index 707d38b611..3b4bf5fb2e 100644 --- a/src/northbridge/intel/i82830/raminit.h +++ b/src/northbridge/intel/i82830/raminit.h @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2008 Joseph Smith <joe@smittys.pointclark.net> + * Copyright (C) 2008-2010 Joseph Smith <joe@settoplinux.org> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -21,12 +21,13 @@ #ifndef NORTHBRIDGE_INTEL_I82830_RAMINIT_H #define NORTHBRIDGE_INTEL_I82830_RAMINIT_H +/* 82830 Northbridge PCI device */ +#define NORTHBRIDGE PCI_DEV(0, 0, 0) + /* The 82830 supports max. 2 dual-sided SO-DIMMs. */ #define DIMM_SOCKETS 2 -struct mem_controller { - device_t d0; - uint16_t channel0[DIMM_SOCKETS]; -}; +/* DIMM0 is at 0x50, DIMM1 is at 0x51. */ +#define DIMM_SPD_BASE 0x50 #endif /* NORTHBRIDGE_INTEL_I82830_RAMINIT_H */ |