diff options
| author | Martin Roth <gaumless@gmail.com> | 2017-10-15 15:14:38 -0600 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2018-01-15 23:25:26 +0000 |
| commit | 0a19b080ef03ba50d111bd966c45ca90cf1507d6 (patch) | |
| tree | b047d42cd509f584d759ab2cac01457e150f5d54 /src/northbridge/intel/i82830/i82830.h | |
| parent | 264566c177dac98e67c2a4765fe08c5d8de10753 (diff) | |
Intel i82830 boards & chips: Remove - using LATE_CBMEM_INIT
All boards and chips that are still using LATE_CBMEM_INIT are being
removed as previously discussed.
If these boards and chips are updated to not use LATE_CBMEM_INIT, they
can be restored to the active codebase from the 4.7 branch.
chips:
cpu/intel/socket_mFCBGA479
northbridge/intel/i82830
Mainboards:
mainboard/rca/rm4100
mainboard/thomson/ip1000
Change-Id: I9574179516c30bb0d6a29741254293c2cc6f12e9
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/22032
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/northbridge/intel/i82830/i82830.h')
| -rw-r--r-- | src/northbridge/intel/i82830/i82830.h | 52 |
1 files changed, 0 insertions, 52 deletions
diff --git a/src/northbridge/intel/i82830/i82830.h b/src/northbridge/intel/i82830/i82830.h deleted file mode 100644 index a4b0a86c89..0000000000 --- a/src/northbridge/intel/i82830/i82830.h +++ /dev/null @@ -1,52 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 Joseph Smith <joe@smittys.pointclark.net> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef NORTHBRIDGE_INTEL_I82830_I82830_H -#define NORTHBRIDGE_INTEL_I82830_I82830_H - -#define RRBAR 0x48 /* Register Range Base Address (0x00000000) */ -#define GCC0 0x50 /* GMCH Control #0 (0xa072) */ -#define GCC1 0x52 /* GMCH Control #1 (0x0000) */ -#define FDHC 0x58 /* Fixed DRAM Hole Control (0x00) */ -#define PAM0 0x59 /* Programmable Attribute Map #0 (0x00) */ -#define PAM1 0x5a /* Programmable Attribute Map #1 (0x00) */ -#define PAM2 0x5b /* Programmable Attribute Map #2 (0x00) */ -#define PAM3 0x5c /* Programmable Attribute Map #3 (0x00) */ -#define PAM4 0x5d /* Programmable Attribute Map #4 (0x00) */ -#define PAM5 0x5e /* Programmable Attribute Map #5 (0x00) */ -#define PAM6 0x5f /* Programmable Attribute Map #6 (0x00) */ -#define DRB 0x60 /* DRAM Row Boundary #0 (0x00) */ -#define DRB1 0x61 /* DRAM Row Boundary #1 (0x00) */ -#define DRB2 0x62 /* DRAM Row Boundary #2 (0x00) */ -#define DRB3 0x63 /* DRAM Row Boundary #3 (0x00) */ -#define DRA 0x70 /* DRAM Row Attribute #0 (0xff) */ -#define DRA1 0x71 /* DRAM Row Attribute #1 (0xff) */ -#define DRT 0x78 /* DRAM Timing (0x00000010) */ -#define DRC 0x7c /* DRAM Controller Mode #0 (0x00000000) */ -#define DRC1 0x7d /* DRAM Controller Mode #1 (0x00000000) */ -#define DRC2 0x7e /* DRAM Controller Mode #2 (0x00000000) */ -#define DRC3 0x7f /* DRAM Controller Mode #3 (0x00000000) */ -#define DTC 0x8c /* DRAM Throttling Control (0x00000000) */ -#define SMRAM 0x90 /* System Management RAM Control (0x02) */ -#define ESMRAMC 0x91 /* Extended System Management RAM Control Reg. (0x38) */ -#define ERRSTS 0x92 /* Error Status (0x0000) */ -#define ERRCMD 0x94 /* Error Command (0x0000) */ -#define BUFF_SC 0xec /* System Memory Buffer Strength Control (0x00000000) */ -#define APBASE 0x10 /* Aperture Base Configuration (0x00000008) */ -#define APSIZE 0xb4 /* Aperture Size (0x00) */ -#define ATTBASE 0xb8 /* Aperture Translation Table Base (0x00000000) */ - -#endif /* NORTHBRIDGE_INTEL_I82830_I82830_H */ |