diff options
| author | Uwe Hermann <uwe@hermann-uwe.de> | 2008-11-20 23:18:10 +0000 |
|---|---|---|
| committer | Uwe Hermann <uwe@hermann-uwe.de> | 2008-11-20 23:18:10 +0000 |
| commit | 4cf5ecf39d58751cbddbbeb3133886acaecc9550 (patch) | |
| tree | 2216cf6194d51cfa3d0be66f4bc35951c8ea1e57 /src/northbridge/intel/i82810/raminit.h | |
| parent | 76c6c95c1ee3d231ee861afba8dbc341f4c02e07 (diff) | |
Get rid of the unnecessary indirection by 'struct mem_controller' for the
Intel 810 chipset (and all boards using it). This isn't required for this
chipset as there's only one memory controller.
This also helps a lot with romcc register usage, you should see the dreaded
"too few registers" less often.
Build-tested with all three boards using the Intel 810 chipset.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Corey Osgood <corey.osgood@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3764 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/northbridge/intel/i82810/raminit.h')
| -rw-r--r-- | src/northbridge/intel/i82810/raminit.h | 6 |
1 files changed, 2 insertions, 4 deletions
diff --git a/src/northbridge/intel/i82810/raminit.h b/src/northbridge/intel/i82810/raminit.h index 1e79397288..5a06dd171d 100644 --- a/src/northbridge/intel/i82810/raminit.h +++ b/src/northbridge/intel/i82810/raminit.h @@ -24,10 +24,8 @@ /* The 82810 supports max. 2 dual-sided DIMMs. */ #define DIMM_SOCKETS 2 -struct mem_controller { - device_t d0; - uint16_t channel0[DIMM_SOCKETS]; -}; +/* DIMM0 is at 0x50, DIMM1 is at 0x51. */ +#define DIMM_SPD_BASE 0x50 /* The following table has been bumped over to this header to avoid clutter in * raminit.c. It's used to translate the value read from SPD Byte 31 to a value |