diff options
| author | Uwe Hermann <uwe@hermann-uwe.de> | 2007-06-19 22:47:11 +0000 |
|---|---|---|
| committer | Uwe Hermann <uwe@hermann-uwe.de> | 2007-06-19 22:47:11 +0000 |
| commit | dfb3c130d5cdd3a01531c23c3d15e7a1010bf221 (patch) | |
| tree | 625092b43a0c3ac24fa359eb14df0f922f81e6ad /src/northbridge/intel/i82810/i82810.h | |
| parent | c72ff11281233c097441e809a52b560b1a131196 (diff) | |
Various minor cosmetics and coding style fixes (trivial).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2727 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/northbridge/intel/i82810/i82810.h')
| -rw-r--r-- | src/northbridge/intel/i82810/i82810.h | 28 |
1 files changed, 14 insertions, 14 deletions
diff --git a/src/northbridge/intel/i82810/i82810.h b/src/northbridge/intel/i82810/i82810.h index 0b406cead4..d5979787cb 100644 --- a/src/northbridge/intel/i82810/i82810.h +++ b/src/northbridge/intel/i82810/i82810.h @@ -34,26 +34,26 @@ * should not be touched. */ -#define VID 0x00 /* Vendor Identification */ -#define DID 0x02 /* Device Identification */ -#define PCICMD 0x04 /* PCI Command Register */ -#define PCISTS 0x06 /* PCI Status Register */ -#define RID 0x08 /* Revision Identification */ -#define SUBC 0x0a /* Sub-Class Code */ -#define BCC 0x0b /* Base Class Code */ -#define MLT 0x0d /* Master Latency Timer */ -#define HDR 0x0e /* Header Type */ -#define SVID 0x2c /* Subsystem Vendor Identification */ -#define SID 0x2e /* Subsystem Identification */ -#define CAPPTR 0x34 /* Capabilities Pointer */ +#define VID 0x00 /* Vendor Identification */ +#define DID 0x02 /* Device Identification */ +#define PCICMD 0x04 /* PCI Command Register */ +#define PCISTS 0x06 /* PCI Status Register */ +#define RID 0x08 /* Revision Identification */ +#define SUBC 0x0a /* Sub-Class Code */ +#define BCC 0x0b /* Base Class Code */ +#define MLT 0x0d /* Master Latency Timer */ +#define HDR 0x0e /* Header Type */ +#define SVID 0x2c /* Subsystem Vendor Identification */ +#define SID 0x2e /* Subsystem Identification */ +#define CAPPTR 0x34 /* Capabilities Pointer */ -/* TODO: Descriptions */ +/* TODO: Descriptions. */ #define GMCHCFG 0x50 #define PAM 0x51 #define DRP 0x52 #define DRAMT 0x53 #define FDHC 0x58 -#define SMRAM 0x70 /* System Management RAM Control */ +#define SMRAM 0x70 /* System Management RAM Control */ #define MISSC 0x72 #define MISSC2 0x80 #define BUFF_SC 0x92 |