diff options
| author | Elia Yehuda <z4ziggy@gmail.com> | 2009-07-05 15:50:30 +0000 |
|---|---|---|
| committer | Uwe Hermann <uwe@hermann-uwe.de> | 2009-07-05 15:50:30 +0000 |
| commit | 76a88d0805a42f3759f1444ab62760f5160fc999 (patch) | |
| tree | 4b49ccbee6f032a5c069e01a2a747aefcd0b3903 /src/northbridge/intel/i82810/i82810.h | |
| parent | bd4f2f808c258bc58814f3a230d0788a0b0fbd26 (diff) | |
Various Intel 82810/82810E changes which allow onboard VGA to work.
At the same time also make the 82810 code handle 82810E.
- Set SMRAM register according to CONFIG_VIDEO_MB value:
- 512 means 512 KB
- 1 means 1 MB
- Every other value for CONFIG_VIDEO_MB (e.g. 0) disables VGA.
This is not very clean, changing CONFIG_VIDEO_MB to CONFIG_VIDEO_KB
in a future patch may be nicer.
- Set MISSC2 register bits as required per datasheet to make VGA work.
The code handles both 82810 and 82810E.
- northbridge.c: Add __pci_driver entry for the Intel 82810E.
Also:
- Rename PAM register #define to PAMR as per datasheet.
- Drop unused/commented code for now.
- Don't explicitly set GMCHCFG for now, the default works ok. We'll
have to figure out the proper/ideal settings later.
The code is based on a patch from Elia Yehuda <z4ziggy@gmail.com> but
has been modified quite a bit for correctness and minimalism.
Tested on hardware with a slightly modified MS-6178 target,
patches to enable onboard-VGA for MS-6178 will follow.
Signed-off-by: Elia Yehuda <z4ziggy@gmail.com>
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4398 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/northbridge/intel/i82810/i82810.h')
| -rw-r--r-- | src/northbridge/intel/i82810/i82810.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/northbridge/intel/i82810/i82810.h b/src/northbridge/intel/i82810/i82810.h index 94993ec540..554302924c 100644 --- a/src/northbridge/intel/i82810/i82810.h +++ b/src/northbridge/intel/i82810/i82810.h @@ -35,7 +35,7 @@ */ #define GMCHCFG 0x50 /* GMCH Configuration */ -#define PAM 0x51 /* Programmable Attributes */ +#define PAMR 0x51 /* Programmable Attributes */ #define DRP 0x52 /* DRAM Row Population */ #define DRAMT 0x53 /* DRAM Timing */ #define FDHC 0x58 /* Fixed DRAM Hole Control */ |