diff options
author | Uwe Hermann <uwe@hermann-uwe.de> | 2010-11-20 20:23:08 +0000 |
---|---|---|
committer | Uwe Hermann <uwe@hermann-uwe.de> | 2010-11-20 20:23:08 +0000 |
commit | d773fd370a92a6da2f7dbf91c085eb0df1f6f30d (patch) | |
tree | fdaa9bd6278f4772c318d105e92a7cfdbc884521 /src/northbridge/intel/i440lx | |
parent | 9bd9a90d6a0a47ede6286e2c5599ae7335e4b96a (diff) |
Some more DIMM0 related cleanups and deduplication.
- VIA VT8235: Do the shift in smbus_read_byte() as all other chipsets do.
- spd.h: Move RC00-RC63 #defines here, they were duplicated in lots of
romstage.c files and lots of spd_addr.h files. Don't even bother for
those spd_addr.h which aren't even actually used, drop them right away.
- Replace various 0x50 hardcoded numbers with DIMM0, 0x51 with DIMM1,
and 0xa0 with (DIMM0 << 1) where appropriate.
- Various debug.c files: Replace SMBUS_MEM_DEVICE_START with DIMM0,
SMBUS_MEM_DEVICE_END with DIMM7, and drop useless SMBUS_MEM_DEVICE_INC.
- VIA VX800: Drop unused SMBUS_ADDR_CH* #defines.
- VIA VT8623: Do the shift in smbus_read_byte() as all other chipsets do.
Then, replace 0xa0 (which now becomes 0x50) with DIMM0.
- alix1c/romstage.c, alix2d/romstage.c: Adapt to recent bit shift changes.
- Various files: Drop DIMM_SPD_BASE and/or replace it with DIMM0.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6100 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/northbridge/intel/i440lx')
-rw-r--r-- | src/northbridge/intel/i440lx/raminit.c | 8 | ||||
-rw-r--r-- | src/northbridge/intel/i440lx/raminit.h | 3 |
2 files changed, 4 insertions, 7 deletions
diff --git a/src/northbridge/intel/i440lx/raminit.c b/src/northbridge/intel/i440lx/raminit.c index dcb22732f2..93fc102f13 100644 --- a/src/northbridge/intel/i440lx/raminit.c +++ b/src/northbridge/intel/i440lx/raminit.c @@ -301,18 +301,18 @@ static void sdram_set_spd_registers(void) PRINT_DEBUG("DIMM"); PRINT_DEBUG_HEX8(i); PRINT_DEBUG(" rows: "); - PRINT_DEBUG_HEX8(spd_read_byte(DIMM_SPD_BASE + i, SPD_NUM_DIMM_BANKS) & 0xFF); + PRINT_DEBUG_HEX8(spd_read_byte(DIMM0 + i, SPD_NUM_DIMM_BANKS) & 0xFF); PRINT_DEBUG(" rowsize: "); - PRINT_DEBUG_HEX8(spd_read_byte(DIMM_SPD_BASE + i, SPD_DENSITY_OF_EACH_ROW_ON_MODULE) & 0xFF); + PRINT_DEBUG_HEX8(spd_read_byte(DIMM0 + i, SPD_DENSITY_OF_EACH_ROW_ON_MODULE) & 0xFF); PRINT_DEBUG(" modulesize: "); - j = spd_read_byte(DIMM_SPD_BASE + i, SPD_NUM_DIMM_BANKS); + j = spd_read_byte(DIMM0 + i, SPD_NUM_DIMM_BANKS); if (j < 0) j = 0; else ds = j; - j = spd_read_byte(DIMM_SPD_BASE + i, SPD_DENSITY_OF_EACH_ROW_ON_MODULE); + j = spd_read_byte(DIMM0 + i, SPD_DENSITY_OF_EACH_ROW_ON_MODULE); if (j < 0) j = 0; diff --git a/src/northbridge/intel/i440lx/raminit.h b/src/northbridge/intel/i440lx/raminit.h index 37331f4374..8dcd02b53b 100644 --- a/src/northbridge/intel/i440lx/raminit.h +++ b/src/northbridge/intel/i440lx/raminit.h @@ -25,7 +25,4 @@ /* The 440LX supports up to four (single- or double-sided) DIMMs. */ #define DIMM_SOCKETS 4 -/* DIMMs 1-4 are at 0x50, 0x51, 0x52, 0x53. */ -#define DIMM_SPD_BASE 0x50 - #endif /* RAMINIT_H */ |