diff options
| author | Uwe Hermann <uwe@hermann-uwe.de> | 2010-11-20 20:23:08 +0000 |
|---|---|---|
| committer | Uwe Hermann <uwe@hermann-uwe.de> | 2010-11-20 20:23:08 +0000 |
| commit | d773fd370a92a6da2f7dbf91c085eb0df1f6f30d (patch) | |
| tree | fdaa9bd6278f4772c318d105e92a7cfdbc884521 /src/northbridge/intel/i440bx | |
| parent | 9bd9a90d6a0a47ede6286e2c5599ae7335e4b96a (diff) | |
Some more DIMM0 related cleanups and deduplication.
- VIA VT8235: Do the shift in smbus_read_byte() as all other chipsets do.
- spd.h: Move RC00-RC63 #defines here, they were duplicated in lots of
romstage.c files and lots of spd_addr.h files. Don't even bother for
those spd_addr.h which aren't even actually used, drop them right away.
- Replace various 0x50 hardcoded numbers with DIMM0, 0x51 with DIMM1,
and 0xa0 with (DIMM0 << 1) where appropriate.
- Various debug.c files: Replace SMBUS_MEM_DEVICE_START with DIMM0,
SMBUS_MEM_DEVICE_END with DIMM7, and drop useless SMBUS_MEM_DEVICE_INC.
- VIA VX800: Drop unused SMBUS_ADDR_CH* #defines.
- VIA VT8623: Do the shift in smbus_read_byte() as all other chipsets do.
Then, replace 0xa0 (which now becomes 0x50) with DIMM0.
- alix1c/romstage.c, alix2d/romstage.c: Adapt to recent bit shift changes.
- Various files: Drop DIMM_SPD_BASE and/or replace it with DIMM0.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6100 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/northbridge/intel/i440bx')
| -rw-r--r-- | src/northbridge/intel/i440bx/debug.c | 2 | ||||
| -rw-r--r-- | src/northbridge/intel/i440bx/raminit.c | 4 | ||||
| -rw-r--r-- | src/northbridge/intel/i440bx/raminit.h | 3 |
3 files changed, 3 insertions, 6 deletions
diff --git a/src/northbridge/intel/i440bx/debug.c b/src/northbridge/intel/i440bx/debug.c index d5748737b6..1d8cbf6a57 100644 --- a/src/northbridge/intel/i440bx/debug.c +++ b/src/northbridge/intel/i440bx/debug.c @@ -7,7 +7,7 @@ void dump_spd_registers(void) print_debug("\n"); for(i = 0; i < DIMM_SOCKETS; i++) { unsigned device; - device = DIMM_SPD_BASE + i; + device = DIMM0 + i; if (device) { int j; print_debug("dimm: "); diff --git a/src/northbridge/intel/i440bx/raminit.c b/src/northbridge/intel/i440bx/raminit.c index 9a5968d592..205d40f4d1 100644 --- a/src/northbridge/intel/i440bx/raminit.c +++ b/src/northbridge/intel/i440bx/raminit.c @@ -616,7 +616,7 @@ static void spd_enable_refresh(void) reg = pci_read_config8(NB, DRAMC); for (i = 0; i < DIMM_SOCKETS; i++) { - value = spd_read_byte(DIMM_SPD_BASE + i, SPD_REFRESH); + value = spd_read_byte(DIMM0 + i, SPD_REFRESH); if (value < 0) continue; reg = (reg & 0xf8) | refresh_rate_map[(value & 0x7f)]; @@ -750,7 +750,7 @@ static void set_dram_row_attributes(void) for (i = 0; i < DIMM_SOCKETS; i++) { unsigned int device; - device = DIMM_SPD_BASE + i; + device = DIMM0 + i; bpr >>= 2; /* First check if a DIMM is actually present. */ diff --git a/src/northbridge/intel/i440bx/raminit.h b/src/northbridge/intel/i440bx/raminit.h index 18268a1e82..4bc07967fd 100644 --- a/src/northbridge/intel/i440bx/raminit.h +++ b/src/northbridge/intel/i440bx/raminit.h @@ -24,9 +24,6 @@ /* The 440BX supports up to four (single- or double-sided) DIMMs. */ #define DIMM_SOCKETS 4 -/* DIMMs 1-4 are at 0x50, 0x51, 0x52, 0x53. */ -#define DIMM_SPD_BASE 0x50 - /* Function prototypes. */ int spd_read_byte(unsigned int device, unsigned int address); void sdram_set_registers(void); |