diff options
| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2018-06-04 08:49:17 +0300 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2018-06-17 19:17:11 +0000 |
| commit | aea8eecded5b51964f72236ea116081123e4a49b (patch) | |
| tree | 5b92f6b6ba6d78f1dfbf1dd277b9b5db5096feec /src/northbridge/intel/i440bx/ram_calc.c | |
| parent | 546990710cbe8a5145d051deaf9e33eeec734c2a (diff) | |
nb/intel/i440bx: Switch to POSTCAR_STAGE
Boot tested on asus/p2b-ls and p2b-ds.
Change-Id: I0154f1d120bef3b45286fb4314f0de419cd8341e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/26821
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge/intel/i440bx/ram_calc.c')
| -rw-r--r-- | src/northbridge/intel/i440bx/ram_calc.c | 12 |
1 files changed, 5 insertions, 7 deletions
diff --git a/src/northbridge/intel/i440bx/ram_calc.c b/src/northbridge/intel/i440bx/ram_calc.c index dc294f14c6..3362d93f48 100644 --- a/src/northbridge/intel/i440bx/ram_calc.c +++ b/src/northbridge/intel/i440bx/ram_calc.c @@ -69,9 +69,10 @@ void *cbmem_top(void) #define ROMSTAGE_RAM_STACK_SIZE 0x5000 -/* setup_stack_and_mtrrs() determines the stack to use after - * cache-as-ram is torn down as well as the MTRR settings to use. */ -void *setup_stack_and_mtrrs(void) +/* platform_enter_postcar() determines the stack to use after + * cache-as-ram is torn down as well as the MTRR settings to use, + * and continues execution in postcar stage. */ +void platform_enter_postcar(void) { struct postcar_frame pcf; uintptr_t top_of_ram; @@ -91,8 +92,5 @@ void *setup_stack_and_mtrrs(void) postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 8*MiB, MTRR_TYPE_WRBACK); - /* Save the number of MTRRs to setup. Return the stack location - * pointing to the number of MTRRs. - */ - return postcar_commit_mtrrs(&pcf); + run_postcar_phase(&pcf); } |