diff options
| author | Keith Hui <buurin@gmail.com> | 2010-03-06 18:16:25 +0000 |
|---|---|---|
| committer | Uwe Hermann <uwe@hermann-uwe.de> | 2010-03-06 18:16:25 +0000 |
| commit | 59356ca48b620b7be431455fa4c3332bc2a25a24 (patch) | |
| tree | cd5f3fa38dfa9b51431d94c0b7cc86a08bab9b76 /src/northbridge/intel/i440bx/i440bx.h | |
| parent | f7b3c5e8524ac4629f5711fa9172259699f36799 (diff) | |
440BX: Do not hardcode DIMM number + size anymore.
The code currently assumes a 4-DIMM-slots board, this will be fixed soon.
Signed-off-by: Keith Hui <buurin@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5194 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/northbridge/intel/i440bx/i440bx.h')
| -rw-r--r-- | src/northbridge/intel/i440bx/i440bx.h | 49 |
1 files changed, 31 insertions, 18 deletions
diff --git a/src/northbridge/intel/i440bx/i440bx.h b/src/northbridge/intel/i440bx/i440bx.h index 0edd41ca4a..97311c5fdf 100644 --- a/src/northbridge/intel/i440bx/i440bx.h +++ b/src/northbridge/intel/i440bx/i440bx.h @@ -32,11 +32,27 @@ * Any addresses between 0x00 and 0xff not listed below are either * Reserved or Intel Reserved and should not be touched. */ + #define NBXCFG 0x50 /* 440BX Configuration (0x0000:00S0_0000_000S_0S00b). */ #define DRAMC 0x57 /* DRAM Control (00S0_0000b). */ #define DRAMT 0x58 /* DRAM Timing (0x03). */ #define PAM 0x59 /* Programmable Attribute Map, 7 registers (0x00). */ +#define PAM0 0x59 +#define PAM1 0x5a +#define PAM2 0x5b +#define PAM3 0x5c +#define PAM4 0x5d +#define PAM5 0x5e +#define PAM6 0x5f #define DRB 0x60 /* DRAM Row Boundary, 8 registers (0x01). */ +#define DRB0 0x60 +#define DRB1 0x61 +#define DRB2 0x62 +#define DRB3 0x63 +#define DRB4 0x64 +#define DRB5 0x65 +#define DRB6 0x66 +#define DRB7 0x67 #define FDHC 0x68 /* Fixed SDRAM Hole Control (0x00). */ #define MBSC 0x69 /* Memory Buffer Strength Control (0x0000-0000-0000). */ #define SMRAM 0x72 /* System Management RAM Control (0x02). */ @@ -50,27 +66,24 @@ #define ERRCMD 0x90 /* Error Command Register (0x80). */ #define ERRSTS 0x91 /* Error Status (0x0000). */ // TODO: AGP stuff. +#define ACAPID 0xa0 /* AGP Capability Identifier (0x00100002 or 0x00000000) */ +#define AGPSTAT 0xa4 /* AGP Status Register (0x1f000203, read only) */ +#define AGPCMD 0xa8 /* AGP Command Register (0x00000000) */ +#define AGPCTRL 0xb0 /* AGP Control Register (0x00000000) */ +#define APSIZE 0xb4 /* Aperture Size Control Register (0x00) */ +#define ATTBASE 0xb8 /* Aperture Translation Table (0x00000000) */ + #define MBFS 0xca /* Memory Buffer Frequency Select (0x000000). */ #define BSPAD 0xd0 /* BIOS Scratch Pad (0x000..000). */ +#define BSPAD0 0xd0 /* These are free for our use. */ +#define BSPAD1 0xd1 +#define BSPAD2 0xd2 +#define BSPAD3 0xd3 +#define BSPAD4 0xd4 +#define BSPAD5 0xd5 +#define BSPAD6 0xd6 +#define BSPAD7 0xd7 #define DWTC 0xe0 /* DRAM Write Thermal Throttling Control (0x000..000). */ #define DRTC 0xe8 /* DRAM Read Thermal Throttling Control (0x000..000). */ #define BUFFC 0xf0 /* Buffer Control Register (0x0000). */ -/* For convenience: */ -#define DRB0 0x60 -#define DRB1 0x61 -#define DRB2 0x62 -#define DRB3 0x63 -#define DRB4 0x64 -#define DRB5 0x65 -#define DRB6 0x66 -#define DRB7 0x67 - -#define PAM0 0x59 -#define PAM1 0x5a -#define PAM2 0x5b -#define PAM3 0x5c -#define PAM4 0x5d -#define PAM5 0x5e -#define PAM6 0x5f - |