diff options
| author | Uwe Hermann <uwe@hermann-uwe.de> | 2007-10-27 19:45:49 +0000 |
|---|---|---|
| committer | Uwe Hermann <uwe@hermann-uwe.de> | 2007-10-27 19:45:49 +0000 |
| commit | 9b80a8d4bc5b49c8921f57c3bf83f04c79817e46 (patch) | |
| tree | 360c9701dd92d40d743690ce0af4016f5ec1f882 /src/northbridge/intel/i440bx/i440bx.h | |
| parent | 65bc460e01c22cf0f347903735d0860756dc0777 (diff) | |
Drop duplicated and unneeded #defines from some northbridges (trivial).
This is generic PCI stuff, not nothbridge-specific in any way.
The respective #defines are already present in src/include/device/pci_def.h.
Abuild-tested, so shouldn't break anything.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2900 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/northbridge/intel/i440bx/i440bx.h')
| -rw-r--r-- | src/northbridge/intel/i440bx/i440bx.h | 13 |
1 files changed, 0 insertions, 13 deletions
diff --git a/src/northbridge/intel/i440bx/i440bx.h b/src/northbridge/intel/i440bx/i440bx.h index 784a8b368a..9932b9b3dd 100644 --- a/src/northbridge/intel/i440bx/i440bx.h +++ b/src/northbridge/intel/i440bx/i440bx.h @@ -32,19 +32,6 @@ * Any addresses between 0x00 and 0xff not listed below are either * Reserved or Intel Reserved and should not be touched. */ -#define VID 0x00 /* Vendor Identification (0x8086). */ -#define DID 0x02 /* Device Identification (0x7190/0x7192). */ -#define PCICMD 0x04 /* PCI Command Register (0x006). */ -#define PCISTS 0x06 /* PCI Status Register (0x0210/0x0200). */ -#define RID 0x08 /* Revision Identification (0x00/0x01/0x02). */ -#define SUBC 0x0a /* Sub-Class Code (0x00). */ -#define BCC 0x0b /* Base Class Code (0x06). */ -#define MLT 0x0d /* Master Latency Timer (0x00). */ -#define HDR 0x0e /* Header Type (0x00). */ -#define APBASE 0x10 /* Aperture Base Configuration (0x00000008). */ -#define SVID 0x2c /* Subsystem Vendor Identification (0x0000). */ -#define SID 0x2e /* Subsystem Identification (0x0000). */ -#define CAPPTR 0x34 /* Capabilities Pointer (0xa0/0x00). */ #define NBXCFG 0x50 /* 440BX Configuration (0x0000:00S0_0000_000S_0S00b). */ #define DRAMC 0x57 /* DRAM Control (00S0_0000b). */ #define DRAMT 0x58 /* DRAM Timing (0x03). */ |