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authorKevin Paul Herbert <kph@meraki.net>2014-12-24 18:43:20 -0800
committerAlexandru Gagniuc <mr.nuke.me@gmail.com>2015-02-15 08:50:22 +0100
commitbde6d309dfafe58732ec46314a2d4c08974b62d4 (patch)
tree17ba00565487ddfbb5759c96adfbb3fffe2a4550 /src/northbridge/intel/i3100
parent4b10dec1a66122b515b2191f823d7fd379ec655f (diff)
x86: Change MMIO addr in readN(addr)/writeN(addr, val) to pointer
On x86, change the type of the address parameter in read8()/read16/read32()/write8()/write16()/write32() to be a pointer, instead of unsigned long. Change-Id: Ic26dd8a72d82828b69be3c04944710681b7bd330 Signed-off-by: Kevin Paul Herbert <kph@meraki.net> Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/7784 Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/northbridge/intel/i3100')
-rw-r--r--src/northbridge/intel/i3100/i3100.h2
-rw-r--r--src/northbridge/intel/i3100/raminit.c9
-rw-r--r--src/northbridge/intel/i3100/raminit_ep80579.c4
3 files changed, 8 insertions, 7 deletions
diff --git a/src/northbridge/intel/i3100/i3100.h b/src/northbridge/intel/i3100/i3100.h
index 2d036bd02d..ac6f8c6b3b 100644
--- a/src/northbridge/intel/i3100/i3100.h
+++ b/src/northbridge/intel/i3100/i3100.h
@@ -65,7 +65,7 @@
#define DRC_72BIT_ECC (1 << 20)
#define RCBA 0xF0
-#define DEFAULT_RCBA 0xFEA00000
+#define DEFAULT_RCBA ((u8 *)0xFEA00000)
int bios_reset_detected(void);
diff --git a/src/northbridge/intel/i3100/raminit.c b/src/northbridge/intel/i3100/raminit.c
index ebe137b909..34d1eefbbe 100644
--- a/src/northbridge/intel/i3100/raminit.c
+++ b/src/northbridge/intel/i3100/raminit.c
@@ -28,7 +28,7 @@
#include "i3100.h"
/* DDR2 memory controller register space */
-#define MCBAR 0x90000000
+#define MCBAR ((u8 *)(0x90000000))
static void sdram_set_registers(const struct mem_controller *ctrl)
{
@@ -61,7 +61,7 @@ static void sdram_set_registers(const struct mem_controller *ctrl)
PCI_ADDR(0, 0x00, 0, DEVPRES1), 0xffbffff, (1<<22)|(6<<2) | DEVPRES1_CONFIG,
/* 0x14 */
- PCI_ADDR(0, 0x00, 0, IURBASE), 0x00000fff, MCBAR |0,
+ PCI_ADDR(0, 0x00, 0, IURBASE), 0x00000fff, (uintptr_t)(MCBAR + 0),
};
int i;
int max;
@@ -936,6 +936,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
int i;
int cs;
int cnt;
+ u8 *cntptr;
int cas_latency;
long mask;
u32 drc;
@@ -1139,8 +1140,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
/* DQS */
pci_write_config32(ctrl->f0, 0x94, 0x3904aa00);
- for(i = 0, cnt = (MCBAR+0x200); i < 24; i++, cnt+=4) {
- write32(cnt, dqs_data[i]);
+ for(i = 0, cntptr = (MCBAR+0x200); i < 24; i++, cnt+=4) {
+ write32(cntptr, dqs_data[i]);
}
pci_write_config32(ctrl->f0, 0x94, 0x3900aa00);
diff --git a/src/northbridge/intel/i3100/raminit_ep80579.c b/src/northbridge/intel/i3100/raminit_ep80579.c
index b2858e4a8f..77d4463e02 100644
--- a/src/northbridge/intel/i3100/raminit_ep80579.c
+++ b/src/northbridge/intel/i3100/raminit_ep80579.c
@@ -25,7 +25,7 @@
#include "raminit_ep80579.h"
#include "ep80579.h"
-#define BAR 0x90000000
+#define BAR ((u8 *)0x90000000)
static void sdram_set_registers(const struct mem_controller *ctrl)
{
@@ -35,7 +35,7 @@ static void sdram_set_registers(const struct mem_controller *ctrl)
PCI_ADDR(0, 0x00, 0, PAM-1), 0xcccccc7f, 0x33333000,
PCI_ADDR(0, 0x00, 0, PAM+3), 0xcccccccc, 0x33333333,
PCI_ADDR(0, 0x00, 0, DEVPRES1), 0xffffffff, 0x0040003a,
- PCI_ADDR(0, 0x00, 0, SMRBASE), 0x00000fff, BAR | 0,
+ PCI_ADDR(0, 0x00, 0, SMRBASE), 0x00000fff, (uintptr_t)BAR | 0,
};
int i;