Support for the memory controller and PCIe interface of the Intel

EP80579 Integrated Processor (codename "Tolapai"). The memory
controller code supports only 64-bit-wide DIMMs with x8 devices and
ECC. It has been tested on a development board using a single Micron
MT9HTF6472PY-667D2 DIMM. Your mileage will definitely vary with other
DIMMs.

Signed-off-by: Ed Swierk <eswierk@arastra.com>
Acked-by: Joseph Smith <joe@settoplinux.org>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3600 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

1 files changed, 31 insertions, 0 deletions

diff --git a/src/northbridge/intel/i3100/raminit_ep80579.h b/src/northbridge/intel/i3100/raminit_ep80579.h
new file mode 100644
index 0000000000..6c9080078c
--- /dev/null
+++ b/src/northbridge/intel/i3100/raminit_ep80579.h
@@ -0,0 +1,31 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Arastra, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ *
+ */
+
+#ifndef NORTHBRIDGE_INTEL_I3100_RAMINIT_EP80579_H
+#define NORTHBRIDGE_INTEL_I3100_RAMINIT_EP80579_H
+
+#define DIMM_SOCKETS 2
+struct mem_controller {
+	u32 node_id;
+	device_t f0;
+	u16 channel0[DIMM_SOCKETS];
+};
+
+#endif