diff options
| author | Kevin Paul Herbert <kph@meraki.net> | 2014-12-24 18:43:20 -0800 |
|---|---|---|
| committer | Alexandru Gagniuc <mr.nuke.me@gmail.com> | 2015-02-15 08:50:22 +0100 |
| commit | bde6d309dfafe58732ec46314a2d4c08974b62d4 (patch) | |
| tree | 17ba00565487ddfbb5759c96adfbb3fffe2a4550 /src/northbridge/intel/i3100/raminit.c | |
| parent | 4b10dec1a66122b515b2191f823d7fd379ec655f (diff) | |
x86: Change MMIO addr in readN(addr)/writeN(addr, val) to pointer
On x86, change the type of the address parameter in
read8()/read16/read32()/write8()/write16()/write32() to be a
pointer, instead of unsigned long.
Change-Id: Ic26dd8a72d82828b69be3c04944710681b7bd330
Signed-off-by: Kevin Paul Herbert <kph@meraki.net>
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/7784
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/northbridge/intel/i3100/raminit.c')
| -rw-r--r-- | src/northbridge/intel/i3100/raminit.c | 9 |
1 files changed, 5 insertions, 4 deletions
diff --git a/src/northbridge/intel/i3100/raminit.c b/src/northbridge/intel/i3100/raminit.c index ebe137b909..34d1eefbbe 100644 --- a/src/northbridge/intel/i3100/raminit.c +++ b/src/northbridge/intel/i3100/raminit.c @@ -28,7 +28,7 @@ #include "i3100.h" /* DDR2 memory controller register space */ -#define MCBAR 0x90000000 +#define MCBAR ((u8 *)(0x90000000)) static void sdram_set_registers(const struct mem_controller *ctrl) { @@ -61,7 +61,7 @@ static void sdram_set_registers(const struct mem_controller *ctrl) PCI_ADDR(0, 0x00, 0, DEVPRES1), 0xffbffff, (1<<22)|(6<<2) | DEVPRES1_CONFIG, /* 0x14 */ - PCI_ADDR(0, 0x00, 0, IURBASE), 0x00000fff, MCBAR |0, + PCI_ADDR(0, 0x00, 0, IURBASE), 0x00000fff, (uintptr_t)(MCBAR + 0), }; int i; int max; @@ -936,6 +936,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) int i; int cs; int cnt; + u8 *cntptr; int cas_latency; long mask; u32 drc; @@ -1139,8 +1140,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) /* DQS */ pci_write_config32(ctrl->f0, 0x94, 0x3904aa00); - for(i = 0, cnt = (MCBAR+0x200); i < 24; i++, cnt+=4) { - write32(cnt, dqs_data[i]); + for(i = 0, cntptr = (MCBAR+0x200); i < 24; i++, cnt+=4) { + write32(cntptr, dqs_data[i]); } pci_write_config32(ctrl->f0, 0x94, 0x3900aa00); |