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authorStefan Reinauer <stepan@coresystems.de>2010-03-31 14:47:43 +0000
committerStefan Reinauer <stepan@openbios.org>2010-03-31 14:47:43 +0000
commit64ed2b73451de4b655b3fdda0ff42825a165c317 (patch)
tree0faaae313a9a9edbf8b33f56fc18830ba14aa75f /src/northbridge/intel/i3100/raminit.c
parent5a1f5970857a5ad1fda0cf9d5945192408bf537b (diff)
Drop \r\n and \n\r as both print_XXX and printk now do this internally.
Only some assembler files still have \r\n ... Can we move that part to C completely? Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5342 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/northbridge/intel/i3100/raminit.c')
-rw-r--r--src/northbridge/intel/i3100/raminit.c32
1 files changed, 16 insertions, 16 deletions
diff --git a/src/northbridge/intel/i3100/raminit.c b/src/northbridge/intel/i3100/raminit.c
index 76475ce235..fa44d599f1 100644
--- a/src/northbridge/intel/i3100/raminit.c
+++ b/src/northbridge/intel/i3100/raminit.c
@@ -76,7 +76,7 @@ static void sdram_set_registers(const struct mem_controller *ctrl)
reg |= register_values[i+2];
pci_write_config32(dev, where, reg);
}
- print_spew("done.\r\n");
+ print_spew("done.\n");
}
struct dimm_size {
@@ -149,7 +149,7 @@ static struct dimm_size spd_get_dimm_size(u16 device)
goto out;
val_err:
- die("Bad SPD value\r\n");
+ die("Bad SPD value\n");
/* If an hw_error occurs report that I have no memory */
hw_err:
sz.side1 = 0;
@@ -277,7 +277,7 @@ static int spd_set_row_attributes(const struct mem_controller *ctrl,
goto out;
val_err:
- die("Bad SPD value\r\n");
+ die("Bad SPD value\n");
/* If an hw_error occurs report that I have no memory */
hw_err:
dra = 0;
@@ -528,7 +528,7 @@ static int spd_set_drt_attributes(const struct mem_controller *ctrl,
}
else {
- die("Invalid SPD 9 bus speed.\r\n");
+ die("Invalid SPD 9 bus speed.\n");
}
/* 0x78 DRT */
@@ -556,7 +556,7 @@ static int spd_set_dram_controller_mode(const struct mem_controller *ctrl,
continue;
}
value = spd_read_byte(ctrl->channel0[cnt], 11); /* ECC */
- if (value != 2) die("ERROR - Non ECC memory dimm\r\n");
+ if (value != 2) die("ERROR - Non ECC memory dimm\n");
value = spd_read_byte(ctrl->channel0[cnt], 12); /*refresh rate*/
value &= 0x0f; /* clip self refresh bit */
@@ -595,7 +595,7 @@ static int spd_set_dram_controller_mode(const struct mem_controller *ctrl,
goto out;
val_err:
- die("Bad SPD value\r\n");
+ die("Bad SPD value\n");
/* If an hw_error occurs report that I have no memory */
hw_err:
drc = 0;
@@ -610,7 +610,7 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl)
/* Test if we can read the spd and if ram is ddr or ddr2 */
dimm_mask = spd_detect_dimms(ctrl);
if (!(dimm_mask & ((1 << DIMM_SOCKETS) - 1))) {
- print_err("No memory for this cpu\r\n");
+ print_err("No memory for this cpu\n");
return;
}
return;
@@ -683,12 +683,12 @@ static void set_on_dimm_termination_enable(const struct mem_controller *ctrl)
data32 = 0x777becdc; /* ESSD */
break;
}
- die("Error - First dimm slot empty\r\n");
+ die("Error - First dimm slot empty\n");
}
print_debug("ODT Value = ");
print_debug_hex32(data32);
- print_debug("\r\n");
+ print_debug("\n");
pci_write_config32(ctrl->f0, DDR2ODTC, data32);
@@ -921,7 +921,7 @@ static void set_receive_enable(const struct mem_controller *ctrl)
print_debug_hex32(recena);
print_debug(", Receive enable B = ");
print_debug_hex32(recenb);
- print_debug("\r\n");
+ print_debug("\n");
/* clear out the calibration area */
write32(MCBAR+DCALDATA+(16*4), 0x00000000);
@@ -977,7 +977,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
0xffffffff, 0xffffffff, 0x000000ff};
mask = spd_detect_dimms(ctrl);
- print_debug("Starting SDRAM Enable\r\n");
+ print_debug("Starting SDRAM Enable\n");
/* 0x80 */
#ifdef DIMM_MAP_LOGICAL
@@ -989,7 +989,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
/* set dram type and Front Side Bus freq. */
drc = spd_set_dram_controller_mode(ctrl, mask);
if( drc == 0) {
- die("Error calculating DRC\r\n");
+ die("Error calculating DRC\n");
}
data32 = drc & ~(3 << 20); /* clear ECC mode */
data32 = data32 & ~(7 << 8); /* clear refresh rates */
@@ -1024,7 +1024,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
for(i=0;i<8;i+=2) { /* loop through each dimm to test */
print_debug("DIMM ");
print_debug_hex8(i);
- print_debug("\r\n");
+ print_debug("\n");
/* Apply NOP */
do_delay();
@@ -1177,7 +1177,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
write32(MCBAR+DCALCSR, 0x0008000f);
/* clear memory and init ECC */
- print_debug("Clearing memory\r\n");
+ print_debug("Clearing memory\n");
for(i=0;i<64;i+=4) {
write32(MCBAR+DCALDATA+i, 0x00000000);
}
@@ -1194,13 +1194,13 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
data32 |= (1 << 31);
pci_write_config32(ctrl->f0, 0x98, data32);
/* wait for completion */
- print_debug("Waiting for mem complete\r\n");
+ print_debug("Waiting for mem complete\n");
while(1) {
data32 = pci_read_config32(ctrl->f0, 0x98);
if( (data32 & (1<<31)) == 0)
break;
}
- print_debug("Done\r\n");
+ print_debug("Done\n");
/* Set initialization complete */
/* 0x7c DRC */