Support for the memory controller and PCIe interface of the Intel

EP80579 Integrated Processor (codename "Tolapai"). The memory
controller code supports only 64-bit-wide DIMMs with x8 devices and
ECC. It has been tested on a development board using a single Micron
MT9HTF6472PY-667D2 DIMM. Your mileage will definitely vary with other
DIMMs.

Signed-off-by: Ed Swierk <eswierk@arastra.com>
Acked-by: Joseph Smith <joe@settoplinux.org>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3600 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

1 files changed, 64 insertions, 0 deletions

diff --git a/src/northbridge/intel/i3100/ep80579.h b/src/northbridge/intel/i3100/ep80579.h
new file mode 100644
index 0000000000..150cbb4528
--- /dev/null
+++ b/src/northbridge/intel/i3100/ep80579.h
@@ -0,0 +1,64 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Arastra, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ *
+ */
+
+#ifndef NORTHBRIDGE_INTEL_I3100_EP80579_H
+#define NORTHBRIDGE_INTEL_I3100_EP80579_H
+
+#define SMRBASE   0x14
+#define MCHCFG0	  0x50
+#define FDHC      0x58
+#define PAM       0x59
+#define DRB       0x60
+#define DRT1      0x64
+#define DRA       0x70
+#define DRT0      0x78
+#define DRC       0x7c
+#define ECCDIAG   0x84
+#define SDRC      0x88
+#define CKDIS     0x8c
+#define CKEDIS    0x8d
+#define DEVPRES   0x9c
+#define  DEVPRES_D0F0 (1 << 0)
+#define  DEVPRES_D1F0 (1 << 1)
+#define  DEVPRES_D2F0 (1 << 2)
+#define  DEVPRES_D3F0 (1 << 3)
+#define  DEVPRES_D4F0 (1 << 4)
+#define  DEVPRES_D10F0 (1 << 5)
+#define EXSMRC    0x9d
+#define SMRAM     0x9e
+#define EXSMRAMC  0x9f
+#define DDR2ODTC  0xb0
+#define TOLM      0xc4
+#define REMAPBASE 0xc6
+#define REMAPLIMIT 0xc8
+#define REMAPOFFSET 0xca
+#define TOM       0xcc
+#define HECBASE   0xce
+#define DEVPRES1  0xf4
+
+#define DCALCSR   0x040
+#define DCALADDR  0x044
+#define DCALDATA  0x048
+#define MBCSR     0x140
+#define MBADDR    0x144
+#define MBDATA    0x148
+#define DDRIOMC2  0x268
+
+#endif