diff options
| author | Aaron Durbin <adurbin@chromium.org> | 2013-03-13 13:51:20 -0500 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2013-03-22 00:13:56 +0100 |
| commit | c0cbd6e8c2bad5453f7c3b6961bc12d03862497a (patch) | |
| tree | 0555d58b3ff09a5cc1eb7435b973e3d75a0095cb /src/northbridge/intel/haswell | |
| parent | dd4a6d2357decf0cf505370234b378985c68f97f (diff) | |
haswell: use dynamic cbmem
Convert the existing haswell code to support reloctable ramstage
to use dynamic cbmem. This patch always selects DYNAMIC_CBMEM as
this option is a hard requirement for relocatable ramstage.
Aside from converting a few new API calls, a cbmem_top()
implementation is added which is defined to be at the begining of the
TSEG region. Also, use the dynamic cbmem library for allocating a
stack in ram for romstage after CAR is torn down.
Utilizing dynamic cbmem does mean that the cmem field in the gnvs
chromeos acpi table is now 0. Also, the memconsole driver in the kernel
won't be able to find the memconsole because the cbmem structure
changed.
Change-Id: I7cf98d15b97ad82abacfb36ec37b004ce4605c38
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/2850
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/northbridge/intel/haswell')
| -rw-r--r-- | src/northbridge/intel/haswell/northbridge.c | 10 | ||||
| -rw-r--r-- | src/northbridge/intel/haswell/raminit.c | 5 |
2 files changed, 13 insertions, 2 deletions
diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c index 53c2f366c2..b57b28e632 100644 --- a/src/northbridge/intel/haswell/northbridge.c +++ b/src/northbridge/intel/haswell/northbridge.c @@ -543,6 +543,16 @@ static void northbridge_init(struct device *dev) MCHBAR32(0x5500) = 0x00100001; } +void *cbmem_top(void) +{ + u32 reg; + + /* The top the reserve regions fall just below the TSEG region. */ + reg = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0, 0)), TSEG); + + return (void *)(reg & ~((1 << 20) - 1)); +} + static void northbridge_enable(device_t dev) { #if CONFIG_HAVE_ACPI_RESUME diff --git a/src/northbridge/intel/haswell/raminit.c b/src/northbridge/intel/haswell/raminit.c index 9a9bb1c09f..c1095a7eb7 100644 --- a/src/northbridge/intel/haswell/raminit.c +++ b/src/northbridge/intel/haswell/raminit.c @@ -202,9 +202,10 @@ void sdram_initialize(struct pei_data *pei_data) report_memory_config(); } -struct cbmem_entry *get_cbmem_toc(void) +void *cbmem_top(void) { - return (struct cbmem_entry *)(get_top_of_ram() - HIGH_MEMORY_SIZE); + /* Top of cbmem is at lowest usable DRAM address below 4GiB. */ + return (void *)get_top_of_ram(); } unsigned long get_top_of_ram(void) |