nb/intel/haswell: Move SPD addresses to devicetree

Introduce a sandybridge-style devicetree setting for SPD addresses,
and use it instead of runtime code in mb_get_spd_map() for all
haswell boards without CONFIG(HAVE_SPD_IN_CBFS) - effectively all
boards except google/slippy.

Patch also covers recently added Z97 boards using Broadwell MRC.

Also update util/autoport to match.

abuild passes for all affected boards.
autoport builds, but otherwise untested.

Change-Id: I574aec9cb6a47c8aaf275ae06c7e1fb695534b34
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79025
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

7 files changed, 26 insertions, 5 deletions

diff --git a/src/northbridge/intel/haswell/Makefile.mk b/src/northbridge/intel/haswell/Makefile.mk
index 8da72dcb1d..bc8cf42046 100644
--- a/src/northbridge/intel/haswell/Makefile.mk
+++ b/src/northbridge/intel/haswell/Makefile.mk
@@ -16,6 +16,7 @@ romstage-y += memmap.c
 romstage-y += romstage.c
 romstage-y += early_init.c
 romstage-y += report_platform.c
+romstage-y += raminit_shared.c
 
 postcar-y += memmap.c
 
diff --git a/src/northbridge/intel/haswell/broadwell_mrc/raminit.c b/src/northbridge/intel/haswell/broadwell_mrc/raminit.c
index 0bb6f28a6a..1ed4248594 100644
--- a/src/northbridge/intel/haswell/broadwell_mrc/raminit.c
+++ b/src/northbridge/intel/haswell/broadwell_mrc/raminit.c
@@ -374,9 +374,8 @@ void perform_raminit(const int s3resume)
 	/* Broadwell MRC uses ACPI values for boot_mode */
 	pei_data.boot_mode = s3resume ? ACPI_S3 : ACPI_S0;
 
-	/* Obtain the SPD addresses from mainboard code */
 	struct spd_info spdi = {0};
-	mb_get_spd_map(&spdi);
+	get_spd_info(&spdi, cfg);
 
 	/*
 	 * Read the SPDs over SMBus in coreboot code so that the data can be used to
diff --git a/src/northbridge/intel/haswell/chip.h b/src/northbridge/intel/haswell/chip.h
index 274e549e2d..dc71340bd6 100644
--- a/src/northbridge/intel/haswell/chip.h
+++ b/src/northbridge/intel/haswell/chip.h
@@ -39,6 +39,8 @@ struct northbridge_intel_haswell_config {
 	bool usb_xhci_on_resume;
 
 	struct i915_gpu_controller_info gfx;
+
+	u8 spd_addresses[4];
 };
 
 #endif /* NORTHBRIDGE_INTEL_HASWELL_CHIP_H */
diff --git a/src/northbridge/intel/haswell/haswell_mrc/raminit.c b/src/northbridge/intel/haswell/haswell_mrc/raminit.c
index 52bb3b1d65..9a7b7fe2d4 100644
--- a/src/northbridge/intel/haswell/haswell_mrc/raminit.c
+++ b/src/northbridge/intel/haswell/haswell_mrc/raminit.c
@@ -391,9 +391,8 @@ void perform_raminit(const int s3resume)
 	/* MRC has hardcoded assumptions of 2 meaning S3 wake. Normalize it here. */
 	pei_data.boot_mode = s3resume ? 2 : 0;
 
-	/* Obtain the SPD addresses from mainboard code */
 	struct spd_info spdi = {0};
-	mb_get_spd_map(&spdi);
+	get_spd_info(&spdi, cfg);
 
 	/* MRC expects left-aligned SMBus addresses, and 0xff for memory-down */
 	for (size_t i = 0; i < ARRAY_SIZE(spdi.addresses); i++) {
diff --git a/src/northbridge/intel/haswell/native_raminit/spd_bitmunching.c b/src/northbridge/intel/haswell/native_raminit/spd_bitmunching.c
index eff993800b..c53ea12320 100644
--- a/src/northbridge/intel/haswell/native_raminit/spd_bitmunching.c
+++ b/src/northbridge/intel/haswell/native_raminit/spd_bitmunching.c
@@ -5,6 +5,7 @@
 #include <console/console.h>
 #include <device/dram/ddr3.h>
 #include <device/smbus_host.h>
+#include <northbridge/intel/haswell/chip.h>
 #include <northbridge/intel/haswell/haswell.h>
 #include <northbridge/intel/haswell/raminit.h>
 #include <string.h>
@@ -70,8 +71,9 @@ static void get_spd_for_dimm(struct raminit_dimm_info *const dimm, const uint8_t
 
 static void get_spd_data(struct sysinfo *ctrl)
 {
+	const struct northbridge_intel_haswell_config *cfg = config_of_soc();
 	struct spd_info spdi = {0};
-	mb_get_spd_map(&spdi);
+	get_spd_info(&spdi, cfg);
 	const uint8_t *cbfs_spd = get_spd_data_from_cbfs(&spdi);
 	for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
 		for (uint8_t slot = 0; slot < NUM_SLOTS; slot++) {
diff --git a/src/northbridge/intel/haswell/raminit.h b/src/northbridge/intel/haswell/raminit.h
index e151b46d8b..6c76739e77 100644
--- a/src/northbridge/intel/haswell/raminit.h
+++ b/src/northbridge/intel/haswell/raminit.h
@@ -4,6 +4,7 @@
 #define NORTHBRIDGE_INTEL_HASWELL_RAMINIT_H
 
 #include <types.h>
+#include "chip.h"
 
 #define SPD_MEMORY_DOWN	0xff
 
@@ -15,6 +16,7 @@ struct spd_info {
 /* Mainboard callback to fill in the SPD addresses */
 void mb_get_spd_map(struct spd_info *spdi);
 
+void get_spd_info(struct spd_info *spdi, const struct northbridge_intel_haswell_config *cfg);
 void perform_raminit(const int s3resume);
 
 #endif	/* NORTHBRIDGE_INTEL_HASWELL_RAMINIT_H */
diff --git a/src/northbridge/intel/haswell/raminit_shared.c b/src/northbridge/intel/haswell/raminit_shared.c
new file mode 100644
index 0000000000..90fe1145cc
--- /dev/null
+++ b/src/northbridge/intel/haswell/raminit_shared.c
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <string.h>
+#include "chip.h"
+#include "raminit.h"
+
+void get_spd_info(struct spd_info *spdi, const struct northbridge_intel_haswell_config *cfg)
+{
+	if (CONFIG(HAVE_SPD_IN_CBFS)) {
+		/* With memory down: from mainboard code */
+		mb_get_spd_map(spdi);
+	} else {
+		/* Without memory down: from devicetree */
+		memcpy(spdi->addresses, cfg->spd_addresses, ARRAY_SIZE(spdi->addresses));
+	}
+}