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| author | Amanda Huang <amanda_hwang@compal.corp-partner.google.com> | 2021-05-27 11:27:18 +0800 |
|---|---|---|
| committer | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2021-06-03 15:51:12 +0000 |
| commit | 4f870594aa119b02d8154d52173b03c1f7de5679 (patch) | |
| tree | 1043af78e14d01cc3bb6bc4d4073a910a4c57bc2 /src/northbridge/intel/haswell | |
| parent | 890702f368a0a8bd6c2b7d56960bdcc65f5f8061 (diff) | |
util/spd_tools: Modify MT53E1G32D2NP-046 WT:B LPDDR4 config
CB:52586 ("util/spd_tools: Add MT53E1G32D2NP-046 WT:B LPDDR4 config")
incorrectly set ranks per channel to 1. However, MT53E1G32D2NP-046 WT:B
part has 2 channels per die and 2 physical dies. Each channel in each die shares DQ-DQS lines with the channel in other die and uses separate CS lines. Thus, number of ranks per channel is 2.
This change fixes the attribute ranksPerChannel for MT53E1G32D2NP-046 WT:B in LP4x global config by setting it to 2.
BUG=b:186616388
Change-Id: Iba87754ca04c2e026a9cbc8ef07412b467140cba
Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55000
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/northbridge/intel/haswell')
0 files changed, 0 insertions, 0 deletions