diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2020-07-03 14:46:47 +0200 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2020-07-12 09:58:33 +0000 |
| commit | 45f448f4a4e09b270d964c98d3aced2e73d9d6bc (patch) | |
| tree | d217f38c8a28fbf1c449f17f243b73a7f23db6dd /src/northbridge/intel/haswell | |
| parent | c05c2b3fb25ca42a75ecc987178c298f7fe0ead5 (diff) | |
haswell: Relocate `mainboard_romstage_entry` to northbridge
This is what sandybridge does, and if done properly allows factoring out
common settings. Said refactoring will be handled in subsequent commits.
Change-Id: I075eba1324a9e7cbd47e776b097eb940102ef4fe
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43108
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
Diffstat (limited to 'src/northbridge/intel/haswell')
| -rw-r--r-- | src/northbridge/intel/haswell/haswell.h | 2 | ||||
| -rw-r--r-- | src/northbridge/intel/haswell/raminit.h | 3 | ||||
| -rw-r--r-- | src/northbridge/intel/haswell/romstage.c | 19 |
3 files changed, 16 insertions, 8 deletions
diff --git a/src/northbridge/intel/haswell/haswell.h b/src/northbridge/intel/haswell/haswell.h index 6eb8de5ea1..baa4f32614 100644 --- a/src/northbridge/intel/haswell/haswell.h +++ b/src/northbridge/intel/haswell/haswell.h @@ -189,8 +189,6 @@ void intel_northbridge_haswell_finalize_smm(void); -struct pei_data; -void romstage_common(struct pei_data *pei_data); void mb_late_romstage_setup(void); /* optional */ void haswell_early_initialization(void); diff --git a/src/northbridge/intel/haswell/raminit.h b/src/northbridge/intel/haswell/raminit.h index 920ee0fabd..140ea2088d 100644 --- a/src/northbridge/intel/haswell/raminit.h +++ b/src/northbridge/intel/haswell/raminit.h @@ -8,6 +8,9 @@ /* Optional function to copy SPD data for on-board memory */ void copy_spd(struct pei_data *peid); +/* Necessary function to initialize pei_data with mainboard-specific settings */ +void mainboard_fill_pei_data(struct pei_data *pei_data); + void sdram_initialize(struct pei_data *pei_data); void setup_sdram_meminfo(struct pei_data *pei_data); int fixup_haswell_errata(void); diff --git a/src/northbridge/intel/haswell/romstage.c b/src/northbridge/intel/haswell/romstage.c index 46633d1817..b2f8e23b71 100644 --- a/src/northbridge/intel/haswell/romstage.c +++ b/src/northbridge/intel/haswell/romstage.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <arch/romstage.h> #include <console/console.h> #include <cf9_reset.h> #include <timestamp.h> @@ -22,10 +23,16 @@ void __weak mb_late_romstage_setup(void) { } -void romstage_common(struct pei_data *pei_data) +/* The romstage entry point for this platform is not mainboard-specific, hence the name */ +void mainboard_romstage_entry(void) { int wake_from_s3; + struct pei_data pei_data = { + }; + + mainboard_fill_pei_data(&pei_data); + enable_lapic(); wake_from_s3 = early_pch_init(); @@ -52,15 +59,15 @@ void romstage_common(struct pei_data *pei_data) post_code(0x3a); /* MRC has hardcoded assumptions of 2 meaning S3 wake. Normalize it here. */ - pei_data->boot_mode = wake_from_s3 ? 2 : 0; + pei_data.boot_mode = wake_from_s3 ? 2 : 0; timestamp_add_now(TS_BEFORE_INITRAM); report_platform_info(); - copy_spd(pei_data); + copy_spd(&pei_data); - sdram_initialize(pei_data); + sdram_initialize(&pei_data); timestamp_add_now(TS_AFTER_INITRAM); @@ -71,7 +78,7 @@ void romstage_common(struct pei_data *pei_data) if (!wake_from_s3) { cbmem_initialize_empty(); /* Save data returned from MRC on non-S3 resumes. */ - save_mrc_data(pei_data); + save_mrc_data(&pei_data); } else if (cbmem_initialize()) { #if CONFIG(HAVE_ACPI_RESUME) /* Failed S3 resume, reset to come up cleanly */ @@ -81,7 +88,7 @@ void romstage_common(struct pei_data *pei_data) haswell_unhide_peg(); - setup_sdram_meminfo(pei_data); + setup_sdram_meminfo(&pei_data); romstage_handoff_init(wake_from_s3); |