diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2021-01-28 13:56:18 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-02-05 09:39:08 +0000 |
| commit | 6e732d34a0c1b87803925065b66076599c1e5642 (patch) | |
| tree | 2e3d33bc34b934edab5ebd0a5af9146b9ec8f482 /src/northbridge/intel/haswell | |
| parent | 6e0ca68c82fe2285e7f6c8fc22711d4a4c65aa2a (diff) | |
intel: Turn `DEFAULT_RCBA` into a Kconfig symbol
Create `FIXED_RCBA_MMIO_BASE` and use it everywhere, except in cases
where a pointer cast would be necessary. Instances in Sandy Bridge MRC
code were left as-is intentionally, so as not to collide with another
cleanup patch train.
Tested with BUILD_TIMELESS=1, these boards remain identical:
- Asus P8Z77-V LX2
- Packard Bell MS2290
Change-Id: I642958fbd6f02dbf54812d6a75d6bc3087acc77a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50036
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge/intel/haswell')
| -rw-r--r-- | src/northbridge/intel/haswell/acpi/hostbridge.asl | 3 | ||||
| -rw-r--r-- | src/northbridge/intel/haswell/northbridge.c | 2 | ||||
| -rw-r--r-- | src/northbridge/intel/haswell/romstage.c | 2 |
3 files changed, 3 insertions, 4 deletions
diff --git a/src/northbridge/intel/haswell/acpi/hostbridge.asl b/src/northbridge/intel/haswell/acpi/hostbridge.asl index 9a39647c06..50a130694f 100644 --- a/src/northbridge/intel/haswell/acpi/hostbridge.asl +++ b/src/northbridge/intel/haswell/acpi/hostbridge.asl @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include "../haswell.h" -#include <southbridge/intel/common/rcba.h> Name (_HID, EISAID ("PNP0A08")) // PCIe Name (_CID, EISAID ("PNP0A03")) // PCI @@ -175,7 +174,7 @@ Device (PDRC) Name (_UID, 1) Name (PDRS, ResourceTemplate () { - Memory32Fixed (ReadWrite, DEFAULT_RCBA, 0x00004000) + Memory32Fixed (ReadWrite, CONFIG_FIXED_RCBA_MMIO_BASE, 0x00004000) Memory32Fixed (ReadWrite, DEFAULT_MCHBAR, 0x00008000) Memory32Fixed (ReadWrite, DEFAULT_DMIBAR, 0x00001000) Memory32Fixed (ReadWrite, DEFAULT_EPBAR, 0x00001000) diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c index 8af6eb27f0..c2c8143be7 100644 --- a/src/northbridge/intel/haswell/northbridge.c +++ b/src/northbridge/intel/haswell/northbridge.c @@ -511,7 +511,7 @@ static void northbridge_topology_init(void) reg32 &= ~(0xffff << 16); reg32 |= 1 | (2 << 16); DMIBAR32(DMILE1D) = reg32; - DMIBAR64(DMILE1A) = (uintptr_t)DEFAULT_RCBA; + DMIBAR64(DMILE1A) = CONFIG_FIXED_RCBA_MMIO_BASE; DMIBAR64(DMILE2A) = (uintptr_t)DEFAULT_EPBAR; reg32 = DMIBAR32(DMILE2D); diff --git a/src/northbridge/intel/haswell/romstage.c b/src/northbridge/intel/haswell/romstage.c index 3227c02287..f5d500b2fb 100644 --- a/src/northbridge/intel/haswell/romstage.c +++ b/src/northbridge/intel/haswell/romstage.c @@ -56,7 +56,7 @@ void mainboard_romstage_entry(void) .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, .smbusbar = CONFIG_FIXED_SMBUS_IO_BASE, .hpet_address = HPET_ADDR, - .rcba = (uintptr_t)DEFAULT_RCBA, + .rcba = CONFIG_FIXED_RCBA_MMIO_BASE, .pmbase = DEFAULT_PMBASE, .gpiobase = DEFAULT_GPIOBASE, .temp_mmio_base = 0xfed08000, |