diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2020-10-23 10:46:37 +0200 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2020-10-24 20:46:42 +0000 |
| commit | 63837b0af094177902f51ce257265f4a6e374256 (patch) | |
| tree | a039a74ca8b01bbaa3ea25933c2302dfc1f1a1f4 /src/northbridge/intel/haswell | |
| parent | 385ce9f4f8574f3346b430fc72bb58ce4d7f10ce (diff) | |
nb/intel/haswell/finalize.c: Drop obsolete SA PM lock
This register had a lock bit on Sandy Bridge, but does not on Haswell.
Moreover, the bit remains cleared on Asrock B85M Pro4 with coreboot.
Therefore, remove the write to this bit, because it has no effect.
Tested on Asrock B85M Pro4, still boots.
Change-Id: I382a6d69233ced5af069767eb61b56741ed665be
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46678
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge/intel/haswell')
| -rw-r--r-- | src/northbridge/intel/haswell/finalize.c | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/src/northbridge/intel/haswell/finalize.c b/src/northbridge/intel/haswell/finalize.c index bff03440fa..ca10146584 100644 --- a/src/northbridge/intel/haswell/finalize.c +++ b/src/northbridge/intel/haswell/finalize.c @@ -18,7 +18,6 @@ void intel_northbridge_haswell_finalize_smm(void) pci_or_config32(HOST_BRIDGE, TOLUD, 1 << 0); MCHBAR32_OR(MMIO_PAVP_MSG, 1 << 0); /* PAVP */ - MCHBAR32_OR(SAPMCTL, 1UL << 31); /* SA PM */ MCHBAR32_OR(UMAGFXCTL, 1 << 0); /* UMA GFX */ MCHBAR32_OR(VTDTRKLCK, 1 << 0); /* VTDTRK */ MCHBAR32_OR(REQLIM, 1UL << 31); |