diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2020-09-14 15:47:59 +0200 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2020-09-17 20:22:17 +0000 |
| commit | e4156c33bdce1a705769f560263bd6640236702f (patch) | |
| tree | 007688cec7181c21d00e8b16b0000a25b10620fb /src/northbridge/intel/haswell | |
| parent | b8b117c7e72ceb641c14db499a2c004fdfaf64f9 (diff) | |
nb/intel/haswell: Move register headers into a subfolder
Move all files with register definitions into a `registers` subfolder.
Subsequent commits will move the remaining registers into this folder.
Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical.
Change-Id: I143b3c829be44a39e14902255cd4bb13bf02f0c1
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45354
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge/intel/haswell')
| -rw-r--r-- | src/northbridge/intel/haswell/haswell.h | 4 | ||||
| -rw-r--r-- | src/northbridge/intel/haswell/registers/host_bridge.h (renamed from src/northbridge/intel/haswell/hostbridge_regs.h) | 6 | ||||
| -rw-r--r-- | src/northbridge/intel/haswell/registers/mchbar.h (renamed from src/northbridge/intel/haswell/mchbar_regs.h) | 6 |
3 files changed, 8 insertions, 8 deletions
diff --git a/src/northbridge/intel/haswell/haswell.h b/src/northbridge/intel/haswell/haswell.h index 49e31a8e66..136701cca2 100644 --- a/src/northbridge/intel/haswell/haswell.h +++ b/src/northbridge/intel/haswell/haswell.h @@ -18,7 +18,7 @@ /* Device 0:0.0 PCI configuration space (Host Bridge) */ #define HOST_BRIDGE PCI_DEV(0, 0, 0) -#include "hostbridge_regs.h" +#include "registers/host_bridge.h" /* Device 0:2.0 PCI configuration space (Graphics Device) */ @@ -43,7 +43,7 @@ #define MCHBAR32_AND_OR(x, and, or) (MCHBAR32(x) = (MCHBAR32(x) & (and)) | (or)) /* As there are many registers, define them on a separate file */ -#include "mchbar_regs.h" +#include "registers/mchbar.h" #define ARCHDIS 0xff0 /* DMA Remap Engine Policy Control */ #define DMAR_LCKDN (1 << 31) diff --git a/src/northbridge/intel/haswell/hostbridge_regs.h b/src/northbridge/intel/haswell/registers/host_bridge.h index 70e15b74e2..d348fd4a61 100644 --- a/src/northbridge/intel/haswell/hostbridge_regs.h +++ b/src/northbridge/intel/haswell/registers/host_bridge.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef __HASWELL_HOSTBRIDGE_REGS_H__ -#define __HASWELL_HOSTBRIDGE_REGS_H__ +#ifndef __HASWELL_REGISTERS_HOST_BRIDGE_H__ +#define __HASWELL_REGISTERS_HOST_BRIDGE_H__ #define EPBAR 0x40 #define MCHBAR 0x48 @@ -68,4 +68,4 @@ #define CAPID0_B 0xe8 -#endif /* __HASWELL_HOSTBRIDGE_REGS_H__ */ +#endif /* __HASWELL_REGISTERS_HOST_BRIDGE_H__ */ diff --git a/src/northbridge/intel/haswell/mchbar_regs.h b/src/northbridge/intel/haswell/registers/mchbar.h index 5fe15567e5..d6e59abe02 100644 --- a/src/northbridge/intel/haswell/mchbar_regs.h +++ b/src/northbridge/intel/haswell/registers/mchbar.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef __HASWELL_MCHBAR_REGS_H__ -#define __HASWELL_MCHBAR_REGS_H__ +#ifndef __HASWELL_REGISTERS_MCHBAR_H__ +#define __HASWELL_REGISTERS_MCHBAR_H__ /* Register definitions */ #define MAD_CHNL 0x5000 /* Address Decoder Channel Configuration */ @@ -44,4 +44,4 @@ #define DMIVCLIM 0x7000 #define CRDTLCK 0x77fc -#endif /* __HASWELL_MCHBAR_REGS_H__ */ +#endif /* __HASWELL_REGISTERS_MCHBAR_H__ */ |