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authorElyes HAOUAS <ehaouas@noos.fr>2020-08-19 21:41:06 +0200
committerMichael Niewöhner <foss@mniewoehner.de>2020-09-21 16:32:10 +0000
commitdddd1cc6913bd0cbb814b68de7315cb84bfb9c2f (patch)
treee4ad63b1db7fbeaf14ad5bf60046a0ed063b86a5 /src/northbridge/intel/haswell
parent7aa3372ce21565962d4cb1090e1f194b6f33f968 (diff)
src/northbridge: Drop unneeded empty lines
Change-Id: I5f3118f0f855160ed49adc543b6169fccd7520ee Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44593 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge/intel/haswell')
-rw-r--r--src/northbridge/intel/haswell/haswell.h1
-rw-r--r--src/northbridge/intel/haswell/report_platform.c1
2 files changed, 0 insertions, 2 deletions
diff --git a/src/northbridge/intel/haswell/haswell.h b/src/northbridge/intel/haswell/haswell.h
index 44ea9b9858..4bcaaa7728 100644
--- a/src/northbridge/intel/haswell/haswell.h
+++ b/src/northbridge/intel/haswell/haswell.h
@@ -20,7 +20,6 @@
#include "registers/host_bridge.h"
-
/* Device 0:2.0 PCI configuration space (Graphics Device) */
#define MSAC 0x62 /* Multi Size Aperture Control */
diff --git a/src/northbridge/intel/haswell/report_platform.c b/src/northbridge/intel/haswell/report_platform.c
index 8c1b98790c..0b5319bdde 100644
--- a/src/northbridge/intel/haswell/report_platform.c
+++ b/src/northbridge/intel/haswell/report_platform.c
@@ -78,7 +78,6 @@ static void report_pch_info(void)
int i;
u16 dev_id = pci_read_config16(PCH_LPC_DEV, 2);
-
const char *pch_type = "Unknown";
for (i = 0; i < ARRAY_SIZE(pch_table); i++) {
if (pch_table[i].dev_id == dev_id) {