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| author | Eric Lai <ericr_lai@compal.corp-partner.google.com> | 2020-12-21 16:57:49 +0800 |
|---|---|---|
| committer | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2020-12-29 17:25:27 +0000 |
| commit | 4ea47c32b01d1604ec2b4d0b40b433454e62c520 (patch) | |
| tree | dca773b9eff205c27c489ca31e98b3f5016837df /src/northbridge/intel/haswell | |
| parent | bd0fa62b6be176395dc119099236709e52a6203e (diff) | |
soc/intel/alderlake: Update chipset.cb for TCSS and USB
Follow TGL chipset.cb to add alias for TCSS and USB ports.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I803dad0af09b26a55ffb767826ba79cf61de04ca
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48793
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge/intel/haswell')
0 files changed, 0 insertions, 0 deletions