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| author | Felix Held <felix-coreboot@felixheld.de> | 2020-07-30 16:13:35 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2020-07-31 21:05:34 +0000 |
| commit | 42d52947934f20e419e42958ffb4973727a12e9c (patch) | |
| tree | cad36c037fc7c9e3c07f68a7b32fbfb97a127221 /src/northbridge/intel/haswell | |
| parent | 7d6dae68708a6063565eff110f36b36a7e4fc545 (diff) | |
vc/amd/fsp/picasso: document DXIO lane number mapping
Haven't found the official documentation for the DXIO lane mapping on
Pollock, so I had to guess that from the working configurations used in
google/dalboz and amd/cereme.
Change-Id: I53aac0aeba8466ae456f0f935114b587b64eeeaa
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44063
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge/intel/haswell')
0 files changed, 0 insertions, 0 deletions