diff options
| author | Elyes Haouas <ehaouas@noos.fr> | 2024-06-01 18:12:16 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2024-07-10 12:55:46 +0000 |
| commit | e7fa24470dc3b3403eabd757a87cfb993f316b1a (patch) | |
| tree | 6497bd70076905089fc81ed777cbec34486569c0 /src/northbridge/intel/haswell | |
| parent | a9997f891facaf3c855d7f2c9c6840acbf101193 (diff) | |
cbmem_top: Change the return value to uintptr_t
Change-Id: Ib757c0548f6f643747ba8d70228b3d6dfa5182cd
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82752
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Jakub Czapiga <czapiga@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge/intel/haswell')
| -rw-r--r-- | src/northbridge/intel/haswell/memmap.c | 4 |
1 files changed, 1 insertions, 3 deletions
diff --git a/src/northbridge/intel/haswell/memmap.c b/src/northbridge/intel/haswell/memmap.c index 6b75caa861..82e1d6552f 100644 --- a/src/northbridge/intel/haswell/memmap.c +++ b/src/northbridge/intel/haswell/memmap.c @@ -69,12 +69,10 @@ void smm_region(uintptr_t *start, size_t *size) void fill_postcar_frame(struct postcar_frame *pcf) { - uintptr_t top_of_ram; - /* Cache at least 8 MiB below the top of ram, and at most 8 MiB * above top of the ram. This satisfies MTRR alignment requirement * with different TSEG size configurations. */ - top_of_ram = ALIGN_DOWN((uintptr_t)cbmem_top(), 8 * MiB); + const uintptr_t top_of_ram = ALIGN_DOWN(cbmem_top(), 8 * MiB); postcar_frame_add_mtrr(pcf, top_of_ram - 8 * MiB, 16 * MiB, MTRR_TYPE_WRBACK); } |