igd.asl rewrite

Old igd.asl had inconsistent addresses (between _DOD and actual device)
and ghost devices. Any of those is enough to make brightness on windows
fail and make igd.asl out-of-ACPI-spec. Also old code favoured ridiculous
copying of the same thing 6 times per chipset. Leave only hooking up and
chipset-specific part in chipset directory. Move NVS handling and ACPI-spec
parts to a common file.

Change-Id: I556769e5e28b83e7465e3db689e26c8c0ab44757
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/7472
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>

4 files changed, 68 insertions, 285 deletions

diff --git a/src/northbridge/intel/haswell/Kconfig b/src/northbridge/intel/haswell/Kconfig
index f04b5c3cc2..e51ac3cf09 100644
--- a/src/northbridge/intel/haswell/Kconfig
+++ b/src/northbridge/intel/haswell/Kconfig
@@ -26,6 +26,7 @@ config NORTHBRIDGE_INTEL_HASWELL
 	select MMCONF_SUPPORT_DEFAULT
 	select INTEL_DDI
 	select INTEL_DP
+	select INTEL_GMA_ACPI
 
 if NORTHBRIDGE_INTEL_HASWELL
 
diff --git a/src/northbridge/intel/haswell/acpi/igd.asl b/src/northbridge/intel/haswell/acpi/igd.asl
index 8ad70d7968..df8a389797 100644
--- a/src/northbridge/intel/haswell/acpi/igd.asl
+++ b/src/northbridge/intel/haswell/acpi/igd.asl
@@ -22,301 +22,57 @@ Device (GFX0)
 {
 	Name (_ADR, 0x00020000)
 
-	/* Display Output Switching */
-	Method (_DOS, 1)
+	OperationRegion (GFXC, PCI_Config, 0x00, 0x0100)
+	Field (GFXC, DWordAcc, NoLock, Preserve)
 	{
-		/* Windows 2000 and Windows XP call _DOS to enable/disable
-		 * Display Output Switching during init and while a switch
-		 * is already active
-		 */
-		Store (And(Arg0, 7), DSEN)
+		Offset (0x10),
+		BAR0, 64
 	}
 
-	/* We try to support as many i945 systems as possible,
-	 * so keep the number of DIDs flexible.
-	 */
-	Method (_DOD, 0)
+	OperationRegion (GFRG, SystemMemory, And(BAR0, 0xfffffffffffffff0), 0x400000)
+	Field (GFRG, DWordAcc, NoLock, Preserve)
 	{
-		If (LEqual(NDID, 1)) {
-			Name(DOD1, Package() {
-				0xffffffff
-			})
-			Store (Or(0x00010000, DID1), Index(DOD1, 0))
-			Return(DOD1)
-		}
-
-		If (LEqual(NDID, 2)) {
-			Name(DOD2, Package() {
-				0xffffffff,
-				0xffffffff
-			})
-			Store (Or(0x00010000, DID2), Index(DOD2, 0))
-			Store (Or(0x00010000, DID2), Index(DOD2, 1))
-			Return(DOD2)
-		}
-
-		If (LEqual(NDID, 3)) {
-			Name(DOD3, Package() {
-				0xffffffff,
-				0xffffffff,
-				0xffffffff
-			})
-			Store (Or(0x00010000, DID3), Index(DOD3, 0))
-			Store (Or(0x00010000, DID3), Index(DOD3, 1))
-			Store (Or(0x00010000, DID3), Index(DOD3, 2))
-			Return(DOD3)
-		}
-
-		If (LEqual(NDID, 4)) {
-			Name(DOD4, Package() {
-				0xffffffff,
-				0xffffffff,
-				0xffffffff,
-				0xffffffff
-			})
-			Store (Or(0x00010000, DID4), Index(DOD4, 0))
-			Store (Or(0x00010000, DID4), Index(DOD4, 1))
-			Store (Or(0x00010000, DID4), Index(DOD4, 2))
-			Store (Or(0x00010000, DID4), Index(DOD4, 3))
-			Return(DOD4)
-		}
-
-		If (LGreater(NDID, 4)) {
-			Name(DOD5, Package() {
-				0xffffffff,
-				0xffffffff,
-				0xffffffff,
-				0xffffffff,
-				0xffffffff
-			})
-			Store (Or(0x00010000, DID5), Index(DOD5, 0))
-			Store (Or(0x00010000, DID5), Index(DOD5, 1))
-			Store (Or(0x00010000, DID5), Index(DOD5, 2))
-			Store (Or(0x00010000, DID5), Index(DOD5, 3))
-			Store (Or(0x00010000, DID5), Index(DOD5, 4))
-			Return(DOD5)
-		}
-
-		/* Some error happened, but we have to return something */
-		Return (Package() {0x00000400})
-	}
-
-	Device(DD01)
-	{
-		/* Device Unique ID */
-		Method(_ADR, 0, Serialized)
-		{
-			If(LEqual(DID1, 0)) {
-				Return (1)
-			} Else {
-				Return (And(0xffff, DID1))
-			}
-		}
-
-		/* Device Current Status */
-		Method(_DCS, 0)
-		{
-			TRAP(1)
-			If (And(CSTE, 1)) {
-				Return (0x1f)
-			}
-			Return(0x1d)
-		}
-
-		/* Query Device Graphics State */
-		Method(_DGS, 0)
-		{
-			If (And(NSTE, 1)) {
-				Return(1)
-			}
-			Return(0)
-		}
-
-		/* Device Set State */
-		Method(_DSS, 1)
-		{
-			/* If Parameter Arg0 is (1 << 31) | (1 << 30), the
-			 * display switch was completed
-			 */
-			If (LEqual(And(Arg0, 0xc0000000), 0xc0000000)) {
-				Store (NSTE, CSTE)
-			}
-		}
-	}
-
-	Device(DD02)
-	{
-		/* Device Unique ID */
-		Method(_ADR, 0, Serialized)
-		{
-			If(LEqual(DID2, 0)) {
-				Return (2)
-			} Else {
-				Return (And(0xffff, DID2))
-			}
-		}
-
-		/* Device Current Status */
-		Method(_DCS, 0)
-		{
-			TRAP(1)
-			If (And(CSTE, 2)) {
-				Return (0x1f)
-			}
-			Return(0x1d)
-		}
-
-		/* Query Device Graphics State */
-		Method(_DGS, 0)
-		{
-			If (And(NSTE, 2)) {
-				Return(1)
-			}
-			Return(0)
-		}
-
-		/* Device Set State */
-		Method(_DSS, 1)
-		{
-			/* If Parameter Arg0 is (1 << 31) | (1 << 30), the
-			 * display switch was completed
-			 */
-			If (LEqual(And(Arg0, 0xc0000000), 0xc0000000)) {
-				Store (NSTE, CSTE)
-			}
-		}
+		Offset (0x48254),
+			BCLV, 16,
+		Offset (0xc8250),
+			CR1, 32,
+			CR2, 32
 	}
 
-
-	Device(DD03)
+	Name (BRIG, Package (0x12)
 	{
-		/* Device Unique ID */
-		Method(_ADR, 0, Serialized)
-		{
-			If(LEqual(DID3, 0)) {
-				Return (3)
-			} Else {
-				Return (And(0xffff, DID3))
-			}
-		}
-
-		/* Device Current Status */
-		Method(_DCS, 0)
-		{
-			TRAP(1)
-			If (And(CSTE, 4)) {
-				Return (0x1f)
-			}
-			Return(0x1d)
-		}
-
-		/* Query Device Graphics State */
-		Method(_DGS, 0)
-		{
-			If (And(NSTE, 4)) {
-				Return(1)
-			}
-			Return(0)
-		}
-
-		/* Device Set State */
-		Method(_DSS, 1)
-		{
-			/* If Parameter Arg0 is (1 << 31) | (1 << 30), the
-			 * display switch was completed
-			 */
-			If (LEqual(And(Arg0, 0xc0000000), 0xc0000000)) {
-				Store (NSTE, CSTE)
-			}
-		}
-	}
-
-
-	Device(DD04)
+		0x61,
+		0x61,
+		0x2,
+		0x4,
+		0x5,
+		0x7,
+		0x9,
+		0xb,
+		0xd,
+		0x11,
+		0x14,
+		0x17,
+		0x1c,
+		0x20,
+		0x27,
+		0x31,
+		0x41,
+		0x61,
+	})
+
+	Method (XBCM, 1, NotSerialized)
 	{
-		/* Device Unique ID */
-		Method(_ADR, 0, Serialized)
-		{
-			If(LEqual(DID4, 0)) {
-				Return (4)
-			} Else {
-				Return (And(0xffff, DID4))
-			}
-		}
-
-		/* Device Current Status */
-		Method(_DCS, 0)
-		{
-			TRAP(1)
-			If (And(CSTE, 8)) {
-				Return (0x1f)
-			}
-			Return(0x1d)
-		}
-
-		/* Query Device Graphics State */
-		Method(_DGS, 0)
-		{
-			If (And(NSTE, 4)) {
-				Return(1)
-			}
-			Return(0)
-		}
-
-		/* Device Set State */
-		Method(_DSS, 1)
-		{
-			/* If Parameter Arg0 is (1 << 31) | (1 << 30), the
-			 * display switch was completed
-			 */
-			If (LEqual(And(Arg0, 0xc0000000), 0xc0000000)) {
-				Store (NSTE, CSTE)
-			}
-		}
+		Store (ShiftLeft (Arg0, 4), BCLV)
+		Store (0x80000000, CR1)
+		Store (0x061a061a, CR2)
 	}
 
-
-	Device(DD05)
+	Method (XBQC, 0, NotSerialized)
 	{
-		/* Device Unique ID */
-		Method(_ADR, 0, Serialized)
-		{
-			If(LEqual(DID5, 0)) {
-				Return (5)
-			} Else {
-				Return (And(0xffff, DID5))
-			}
-		}
-
-		/* Device Current Status */
-		Method(_DCS, 0)
-		{
-			TRAP(1)
-			If (And(CSTE, 16)) {
-				Return (0x1f)
-			}
-			Return(0x1d)
-		}
-
-		/* Query Device Graphics State */
-		Method(_DGS, 0)
-		{
-			If (And(NSTE, 4)) {
-				Return(1)
-			}
-			Return(0)
-		}
-
-		/* Device Set State */
-		Method(_DSS, 1)
-		{
-			/* If Parameter Arg0 is (1 << 31) | (1 << 30), the
-			 * display switch was completed
-			 */
-			If (LEqual(And(Arg0, 0xc0000000), 0xc0000000)) {
-				Store (NSTE, CSTE)
-			}
-		}
+		Store (BCLV, Local0)
+		ShiftRight (Local0, 4, Local0)
+		Return (Local0)
 	}
-
+#include <drivers/intel/gma/igd.asl>
 }
diff --git a/src/northbridge/intel/haswell/chip.h b/src/northbridge/intel/haswell/chip.h
index 801e062f72..6ae348394d 100644
--- a/src/northbridge/intel/haswell/chip.h
+++ b/src/northbridge/intel/haswell/chip.h
@@ -17,6 +17,8 @@
  * Foundation, Inc.
  */
 
+#include <drivers/intel/gma/i915.h>
+
 /*
  * Digital Port Hotplug Enable:
  *  0x04 = Enabled, 2ms short pulse
@@ -38,6 +40,8 @@ struct northbridge_intel_haswell_config {
 
 	u32 gpu_cpu_backlight;	/* CPU Backlight PWM value */
 	u32 gpu_pch_backlight;	/* PCH Backlight PWM value */
+
+	struct i915_gpu_controller_info gfx;
 };
 
 extern struct chip_operations northbridge_intel_haswell_ops;
diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c
index 6faae2526a..f120670ebc 100644
--- a/src/northbridge/intel/haswell/gma.c
+++ b/src/northbridge/intel/haswell/gma.c
@@ -487,6 +487,27 @@ static void gma_set_subsystem(device_t dev, unsigned vendor, unsigned device)
 	}
 }
 
+const struct i915_gpu_controller_info *
+intel_gma_get_controller_info(void)
+{
+	device_t dev = dev_find_slot(0, PCI_DEVFN(0x2,0));
+	if (!dev) {
+		return NULL;
+	}
+	struct northbridge_intel_haswell_config *chip = dev->chip_info;
+	return &chip->gfx;
+}
+
+static void gma_ssdt(void)
+{
+	const struct i915_gpu_controller_info *gfx = intel_gma_get_controller_info();
+	if (!gfx) {
+		return;
+	}
+
+	drivers_intel_gma_displays_ssdt_generate(gfx);
+}
+
 static struct pci_operations gma_pci_ops = {
 	.set_subsystem    = gma_set_subsystem,
 };
@@ -496,6 +517,7 @@ static struct device_operations gma_func0_ops = {
 	.set_resources		= pci_dev_set_resources,
 	.enable_resources	= pci_dev_enable_resources,
 	.init			= gma_func0_init,
+	.acpi_fill_ssdt_generator = gma_ssdt,
 	.scan_bus		= 0,
 	.enable			= 0,
 	.ops_pci		= &gma_pci_ops,