diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2020-10-28 19:52:22 +0100 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2021-01-10 15:43:10 +0000 |
| commit | 15e5e514613bbf25ca5cd5cba81bde31b4085d0b (patch) | |
| tree | 264840897f5be0ac2855a22c06af01c2af0e74dd /src/northbridge/intel/haswell | |
| parent | 4c95f10232b7287ba187b358056b92ed73980cfa (diff) | |
cpu/intel/haswell/haswell.h: Align with Broadwell
Sort MSR definitions, move MCHBAR registers to northbridge and relocate
C-state latency macros into the header.
Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical.
Change-Id: I3b02f1b1eff522c037e6fc8bb0d831423913da29
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46914
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge/intel/haswell')
| -rw-r--r-- | src/northbridge/intel/haswell/registers/mchbar.h | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/src/northbridge/intel/haswell/registers/mchbar.h b/src/northbridge/intel/haswell/registers/mchbar.h index 97ae433412..4bdb49a370 100644 --- a/src/northbridge/intel/haswell/registers/mchbar.h +++ b/src/northbridge/intel/haswell/registers/mchbar.h @@ -34,6 +34,28 @@ #define MCH_DDR_POWER_LIMIT_HI 0x58e4 #define SSKPD 0x5d10 /* 64-bit scratchpad register */ + +/* PCODE MMIO communications live in the MCHBAR */ +#define BIOS_MAILBOX_DATA 0x5da0 + +#define BIOS_MAILBOX_INTERFACE 0x5da4 +#define MAILBOX_RUN_BUSY (1 << 31) +#define MAILBOX_BIOS_CMD_READ_PCS 1 +#define MAILBOX_BIOS_CMD_WRITE_PCS 2 +#define MAILBOX_BIOS_CMD_READ_CALIBRATION 0x509 +#define MAILBOX_BIOS_CMD_FSM_MEASURE_INTVL 0x909 +#define MAILBOX_BIOS_CMD_READ_PCH_POWER 0xa +#define MAILBOX_BIOS_CMD_READ_PCH_POWER_EXT 0xb +/* Errors are returned back in bits 7:0 */ +#define MAILBOX_BIOS_ERROR_NONE 0 +#define MAILBOX_BIOS_ERROR_INVALID_COMMAND 1 +#define MAILBOX_BIOS_ERROR_TIMEOUT 2 +#define MAILBOX_BIOS_ERROR_ILLEGAL_DATA 3 +#define MAILBOX_BIOS_ERROR_RESERVED 4 +#define MAILBOX_BIOS_ERROR_ILLEGAL_VR_ID 5 +#define MAILBOX_BIOS_ERROR_VR_INTERFACE_LOCKED 6 +#define MAILBOX_BIOS_ERROR_VR_ERROR 7 + #define BIOS_RESET_CPL 0x5da8 /* 8-bit */ #define MC_BIOS_DATA 0x5e04 /* Miscellaneous information for BIOS */ |