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authorAaron Durbin <adurbin@chromium.org>2018-10-31 09:41:59 -0600
committerAaron Durbin <adurbin@chromium.org>2018-11-01 21:33:13 +0000
commit4587f847578beacd7d18d03a6bd5e1d4069e2295 (patch)
tree06ce92e3df750aa62dde1aa9e9f3de148a2169cf /src/northbridge/intel/haswell
parent76ab2b7a8a62e80b0ccdad60f15113fa6d73187f (diff)
arch/x86: clarify raw CAR_GLOBAL access guards
Romstage is where DRAM comes online. Therefore, allow raw CAR_GLOBAL object access in all cache-as-ram stages that are not romstage. In practice, this should be a nop. However, the explicit check for romstage is clearer. Change-Id: I31454c05029140a946ef663b8fa1b2fa6a788154 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/29401 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'src/northbridge/intel/haswell')
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