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authorAaron Durbin <adurbin@chromium.org>2012-10-30 09:03:43 -0500
committerRonald G. Minnich <rminnich@gmail.com>2013-03-14 01:44:40 +0100
commit76c3700f02f79b49fec30d6ef18d336f122cbf50 (patch)
treecb1c750ef3946e2ae462e1847ec89946579274b2 /src/northbridge/intel/haswell/report_platform.c
parentcc86e63e835ab0bceb62215460a13266a791cdd3 (diff)
haswell: Add initial support for Haswell platforms
The Haswell parts use a PCH code named Lynx Point (Series 8). Therefore, the southbridge support is included as well. The basis for this code is the Sandybridge code. Management Engine, IRQ routing, and ACPI still requires more attention, but this is a good starting point. This code partially gets up through the romstage just before training memory on a Haswell reference board. Change-Id: If572d6c21ca051b486b82a924ca0ffe05c4d0ad4 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/2616 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/northbridge/intel/haswell/report_platform.c')
-rw-r--r--src/northbridge/intel/haswell/report_platform.c112
1 files changed, 112 insertions, 0 deletions
diff --git a/src/northbridge/intel/haswell/report_platform.c b/src/northbridge/intel/haswell/report_platform.c
new file mode 100644
index 0000000000..c65bbe5faa
--- /dev/null
+++ b/src/northbridge/intel/haswell/report_platform.c
@@ -0,0 +1,112 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <arch/cpu.h>
+#include <string.h>
+#include "southbridge/intel/lynxpoint/pch.h"
+#include <arch/io.h>
+#include <arch/io.h>
+#include <cpu/x86/msr.h>
+#include <arch/romcc_io.h>
+#include "haswell.h"
+
+static void report_cpu_info(void)
+{
+ struct cpuid_result cpuidr;
+ u32 i, index;
+ char cpu_string[50], *cpu_name = cpu_string; /* 48 bytes are reported */
+ int vt, txt, aes;
+ msr_t microcode_ver;
+ const char *mode[] = {"NOT ", ""};
+
+ index = 0x80000000;
+ cpuidr = cpuid(index);
+ if (cpuidr.eax < 0x80000004) {
+ strcpy(cpu_string, "Platform info not available");
+ } else {
+ u32 *p = (u32*) cpu_string;
+ for (i = 2; i <= 4 ; i++) {
+ cpuidr = cpuid(index + i);
+ *p++ = cpuidr.eax;
+ *p++ = cpuidr.ebx;
+ *p++ = cpuidr.ecx;
+ *p++ = cpuidr.edx;
+ }
+ }
+ /* Skip leading spaces in CPU name string */
+ while (cpu_name[0] == ' ')
+ cpu_name++;
+
+ microcode_ver.lo = 0;
+ microcode_ver.hi = 0;
+ wrmsr(0x8B, microcode_ver);
+ cpuidr = cpuid(1);
+ microcode_ver = rdmsr(0x8b);
+ printk(BIOS_DEBUG, "CPU id(%x) ucode:%08x %s\n", cpuidr.eax, microcode_ver.hi, cpu_name);
+ aes = (cpuidr.ecx & (1 << 25)) ? 1 : 0;
+ txt = (cpuidr.ecx & (1 << 6)) ? 1 : 0;
+ vt = (cpuidr.ecx & (1 << 5)) ? 1 : 0;
+ printk(BIOS_DEBUG, "AES %ssupported, TXT %ssupported, VT %ssupported\n",
+ mode[aes], mode[txt], mode[vt]);
+}
+
+/* The PCI id name match comes from Intel document 472178 */
+static struct {
+ u16 dev_id;
+ const char *dev_name;
+} pch_table [] = {
+ {0x8c41, "Mobile Engineering Sample"},
+ {0x8c42, "Desktop Engineering Sample"},
+ {0x8c46, "Z87"},
+ {0x8c49, "Z85"},
+ {0x8c4a, "HM86"},
+ {0x8c4b, "H87"},
+ {0x8c4c, "Q85"},
+ {0x8c4e, "Q87"},
+ {0x8c4f, "QM87"},
+ {0x8c50, "B85"},
+ {0x8c52, "C222"},
+ {0x8c54, "C224"},
+ {0x8c56, "C226"},
+ {0x8c5c, "H81"},
+};
+
+static void report_pch_info(void)
+{
+ int i;
+ u16 dev_id = pci_read_config16(PCH_LPC_DEV, 2);
+
+
+ const char *pch_type = "Unknown";
+ for (i = 0; i < ARRAY_SIZE(pch_table); i++) {
+ if (pch_table[i].dev_id == dev_id) {
+ pch_type = pch_table[i].dev_name;
+ break;
+ }
+ }
+ printk (BIOS_DEBUG, "PCH type: %s, device id: %x, rev id %x\n",
+ pch_type, dev_id, pci_read_config8(PCH_LPC_DEV, 8));
+}
+
+void report_platform_info(void)
+{
+ report_cpu_info();
+ report_pch_info();
+}