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| author | Duncan Laurie <dlaurie@chromium.org> | 2013-05-22 16:31:09 -0700 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2013-11-25 23:37:48 +0100 |
| commit | 5290f71569d1bf8b6fa80d34f4b176407082fec8 (patch) | |
| tree | e00fc5374ae6dd041745cf6e4a7121185b46087d /src/northbridge/intel/haswell/pei_data.h | |
| parent | 619eca0685ef2c7777ff0d741730a29af5db05a0 (diff) | |
falco: Initial mainboard commit
- Only the first two DIMM SPDs are specified so far
- GPIO map is updated
- iSSD power sequencing removed
- USB port map updated
Change-Id: I4172460d3b075bfd5bb22013a6225cf0e8f95b9c
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/56329
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4184
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/northbridge/intel/haswell/pei_data.h')
0 files changed, 0 insertions, 0 deletions