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author | Felix Held <felix-coreboot@felixheld.de> | 2021-02-05 22:26:00 +0100 |
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committer | Felix Held <felix-coreboot@felixheld.de> | 2021-02-07 17:48:59 +0000 |
commit | 0ffebacfd798279279eae56ce04989735ce4862b (patch) | |
tree | 5e554cd98de4fe2624ba799245ce292639a9f051 /src/northbridge/intel/haswell/pei_data.h | |
parent | 5a7e4a59821905350c1cdfc3ddbf571c041d800e (diff) |
soc/amd/cezanne/pcie_gpp: scan internal PCI buses
TEST=The devices on the internal buses now get resources assigned.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: If7ff0f2ecde9189691548e071ddcfe1916933571
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50334
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/northbridge/intel/haswell/pei_data.h')
0 files changed, 0 insertions, 0 deletions