diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2021-01-20 01:10:48 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-02-12 07:52:25 +0000 |
| commit | f95b9b4b092837663b6fa1cf42ce312338dee5c3 (patch) | |
| tree | f6357a2e6b866a1bad014f17f946cc68b7ecd7e0 /src/northbridge/intel/haswell/northbridge.c | |
| parent | ea573b04d8da056ce41833975cadf58df843c01e (diff) | |
nb/intel/haswell: Use common {DMI,EP,MCH}BAR accessors
Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical.
Change-Id: I3ff4577ce662697cb3d8fb34003217fd6275dd42
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49749
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Diffstat (limited to 'src/northbridge/intel/haswell/northbridge.c')
| -rw-r--r-- | src/northbridge/intel/haswell/northbridge.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c index c2c8143be7..61ad23610e 100644 --- a/src/northbridge/intel/haswell/northbridge.c +++ b/src/northbridge/intel/haswell/northbridge.c @@ -477,7 +477,7 @@ static void northbridge_topology_init(void) reg32 &= ~(0xff << 16); reg32 |= 1 | (1 << 16); EPBAR32(EPLE1D) = reg32; - EPBAR64(EPLE1A) = (uintptr_t)DEFAULT_DMIBAR; + EPBAR64(EPLE1A) = CONFIG_FIXED_DMIBAR_MMIO_BASE; for (unsigned int i = 0; i <= 2; i++) { const struct device *const dev = pcidev_on_root(1, i); @@ -493,7 +493,7 @@ static void northbridge_topology_init(void) EPBAR32(eple_d[i]) = reg32; pci_update_config32(dev, PEG_ESD, ~(0xff << 16), (1 << 16)); - pci_write_config32(dev, PEG_LE1A, (uintptr_t)DEFAULT_EPBAR); + pci_write_config32(dev, PEG_LE1A, CONFIG_FIXED_EPBAR_MMIO_BASE); pci_write_config32(dev, PEG_LE1A + 4, 0); pci_update_config32(dev, PEG_LE1D, ~(0xff << 16), (1 << 16) | 1); @@ -513,7 +513,7 @@ static void northbridge_topology_init(void) DMIBAR32(DMILE1D) = reg32; DMIBAR64(DMILE1A) = CONFIG_FIXED_RCBA_MMIO_BASE; - DMIBAR64(DMILE2A) = (uintptr_t)DEFAULT_EPBAR; + DMIBAR64(DMILE2A) = CONFIG_FIXED_EPBAR_MMIO_BASE; reg32 = DMIBAR32(DMILE2D); reg32 &= ~(0xff << 16); reg32 |= 1 | (1 << 16); |