diff options
| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2013-10-15 17:19:41 +0300 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2014-01-15 15:29:52 +0100 |
| commit | cb08e169cf959333206ef69d8aa82808ef797eb7 (patch) | |
| tree | f025f6d243e815821ae70d8febbdb415025d7dfa /src/northbridge/intel/haswell/northbridge.c | |
| parent | bbf013c38fe76cf9cc107c41c17e4ac432847d28 (diff) | |
CBMEM intel: Define get_top_of_ram() once per chipset
Only have one definition of get_top_of_ram() function and compile
it using __SIMPLE_DEVICE__ for both romstage and ramstage.
Implemented like this on intel/northbridge/gm45 already.
This also adds get_top_of_ram() to i945 ramstage.
Change-Id: Ia82cf6e47a4c929223ea3d8f233d606e6f5bf2f1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3993
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
Diffstat (limited to 'src/northbridge/intel/haswell/northbridge.c')
| -rw-r--r-- | src/northbridge/intel/haswell/northbridge.c | 10 |
1 files changed, 0 insertions, 10 deletions
diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c index bdf87b1616..8d57c03b16 100644 --- a/src/northbridge/intel/haswell/northbridge.c +++ b/src/northbridge/intel/haswell/northbridge.c @@ -449,16 +449,6 @@ static void northbridge_init(struct device *dev) MCHBAR32(0x5500) = 0x00100001; } -unsigned long get_top_of_ram(void) -{ - u32 reg; - - /* The top the reserve regions fall just below the TSEG region. */ - reg = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0, 0)), TSEG); - - return (reg & ~((1 << 20) - 1)); -} - static void northbridge_enable(device_t dev) { #if CONFIG_HAVE_ACPI_RESUME |