diff options
| author | Aaron Durbin <adurbin@chromium.org> | 2013-04-24 17:31:49 -0500 |
|---|---|---|
| committer | Ronald G. Minnich <rminnich@gmail.com> | 2013-05-01 07:11:22 +0200 |
| commit | 243aa44b74935cfc969106dbbe2420ee4a2c39b2 (patch) | |
| tree | 645ee8f1e41ad05d2e29d786c86454bf406f82fa /src/northbridge/intel/haswell/northbridge.c | |
| parent | 40131cfa46bc195ad3bdf2ce9b9af67dcbfd71ca (diff) | |
boot: remove cbmem_post_handling()
The cbmem_post_handling() function was implemented by 2
chipsets in order to save memory configuration in flash. Convert
both of these chipsets to use the boot state machine callbacks
to perform the saving of the memory configuration.
Change-Id: I697e5c946281b85a71d8533437802d7913135af3
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/3137
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/northbridge/intel/haswell/northbridge.c')
| -rw-r--r-- | src/northbridge/intel/haswell/northbridge.c | 5 |
1 files changed, 0 insertions, 5 deletions
diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c index 16196ad6ad..5c1ab3e1ff 100644 --- a/src/northbridge/intel/haswell/northbridge.c +++ b/src/northbridge/intel/haswell/northbridge.c @@ -53,11 +53,6 @@ int bridge_silicon_revision(void) return bridge_revision_id; } -void cbmem_post_handling(void) -{ - update_mrc_cache(); -} - static int get_pcie_bar(device_t dev, unsigned int index, u32 *base, u32 *len) { u32 pciexbar_reg; |