diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2020-08-03 14:12:13 +0200 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2020-08-04 21:28:05 +0000 |
| commit | f4fa1e1d06b5c68b746274c39f23cc8b05801d90 (patch) | |
| tree | 71791abd70eaa3d21b38c284ded82eee8bdf4743 /src/northbridge/intel/haswell/northbridge.c | |
| parent | 90de10c17a2d72065592875b4af206e9cb1a7feb (diff) | |
nb/intel/haswell: Deduplicate PCIEXBAR decoding
Add `decode_pcie_bar` for consistency with other Intel northbridges.
Change-Id: If04ca3467bb067b28605a3acccb8bda325735999
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44120
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/northbridge/intel/haswell/northbridge.c')
| -rw-r--r-- | src/northbridge/intel/haswell/northbridge.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c index 0a5af4fa7b..e1c26d162c 100644 --- a/src/northbridge/intel/haswell/northbridge.c +++ b/src/northbridge/intel/haswell/northbridge.c @@ -51,6 +51,11 @@ static int get_pcie_bar(struct device *dev, unsigned int index, u32 *base, u32 * return 0; } +int decode_pcie_bar(u32 *const base, u32 *const len) +{ + return get_pcie_bar(pcidev_on_root(0, 0), PCIEXBAR, base, len); +} + static const char *northbridge_acpi_name(const struct device *dev) { if (dev->path.type == DEVICE_PATH_DOMAIN) |