diff options
| author | Matt DeVillier <matt.devillier@gmail.com> | 2018-03-04 01:41:23 -0600 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-03-08 17:49:50 +0000 |
| commit | 85d98d9236c006e6ea328e8cde79b5bc15ee1264 (patch) | |
| tree | e1003bcf29ceb23545cdf3cb8dacf117f3b9c847 /src/northbridge/intel/haswell/northbridge.c | |
| parent | 62bef5a6bebbb01f00fd3f11488db749b005087e (diff) | |
nb/intel/haswell: Generate ACPI DMAR table
If the SoC is VT-d capable, write an ACPI DMAR table. The entry for the
GFXVTBAR is only generated if the IGD is enabled.
Change-Id: Ib354337d47b27d18c3b79b5de3b4fa100b59c8fc
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/24984
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Youness Alaoui <snifikino@gmail.com>
Diffstat (limited to 'src/northbridge/intel/haswell/northbridge.c')
| -rw-r--r-- | src/northbridge/intel/haswell/northbridge.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c index 32be916a45..f51eb35ee8 100644 --- a/src/northbridge/intel/haswell/northbridge.c +++ b/src/northbridge/intel/haswell/northbridge.c @@ -85,6 +85,7 @@ static struct device_operations pci_domain_ops = { .init = NULL, .scan_bus = pci_domain_scan_bus, .ops_pci_bus = pci_bus_default_ops, + .write_acpi_tables = northbridge_write_acpi_tables, }; static int get_bar(device_t dev, unsigned int index, u32 *base, u32 *len) |